System and method for use of on-chip non-volatile memory write cache

A memory system comprising:

• an array of non-volatile memory cells on a substrate;
• a controller that determines a physical address in the array of non-volatile memory cells for storing an addressable data packet received from a host;
• and
• a cache memory on the substrate, the cache memory configured to receive and hold the addressable data packet so that the addressable data packet may be updated while in the cache memory, the cache memory configured to program data to the memory array in minimum units of program of the array, the minimum unit of program of the array comprising more than one addressable data packet.

A method of programming a non-volatile memory array with a plurality of received addressable data packets, the memory array having minimum units of programming of a page and minimum units of erase of an erase block, an erase bock being larger than a page and a page being larger than an addressable data packet, comprising:

• receiving an addressable data packet having a logical address from a host;
• selecting a physical address in the non-volatile memory array for writing the addressable data packet;
• recording the relationship between the logical address and the physical address;
• storing the addressable data packet in a cache memory if the cache memory is empty;
• storing a received addressable data packet in a cache memory if there is data in the cache memory and the physical address for writing the data in the cache memory and the physical address for writing the addressable data packet are in a single page of the memory array;
• and
• writing data from the cache memory to the memory array if the physical address for writing the data in the cache memory and the physical address for writing the addressable data packet are not in a single page of the memory array.

A method of updating data in a non-volatile memory array, comprising:

• reading a page of data from a first physical location in the non-volatile memory into a cache, the page of data containing a plurality of addressable units of data;
• receiving an addressable unit of data and comparing the logical address of the received addressable unit of data with the logical addresses of the plurality of addressable units of data;
• if the received addressable unit of data has a logical address that is the logical address of one of the plurality of addressable units of data, then replacing the one of the plurality of addressable unit of data with the received addressable unit of data in the cache;
• and
• subsequently writing the contents of the cache to a second physical location in the non-volatile memory array.

A method of operating a memory system that includes a volatile memory in communication with a non-volatile memory, the non-volatile memory storing data in multi-level cells, the memory system in communication with a host, comprising:

• the memory system receiving a portion of data from the host for storage in the non-volatile memory;
• storing the portion of data in the volatile memory;
• if a low-power condition is not indicated, then maintaining the portion of data in the volatile memory without copying the portion of data to non-volatile memory and waiting for a subsequent command;
• if a low-power condition is indicated, copying the portion of data in the volatile memory to the non-volatile memory and writing the portion of data in the non-volatile memory in binary format.