Flash memory data storage apparatus
AssigneeSamsung Electronics Co., Ltd.
InventorsMin-Gun Park, Jin-Wook Lee
Life of this patent
Estimating the term…
Abstract
In a flash memory data storage apparatus, a multistage flash input buffer unit is embedded in which data bus width is gradually extended and the period of a control clock is gradually made longer. In one example, the flash memory data storage apparatus renders its embedded flash memory to be accessed with 128-bit data in parallel in a period of 80 ns, while communicating with an external system for 16-bit data in parallel during a period of 20 ns. The flash memory data storage apparatus improves a data rate between the flash memory and a buffer memory, resulting in remarkable advancement of the data rate between the flash memory and an external system.
Claims14
A flash memory data storage apparatus that transceives data with an external system through a host bus group in parallel, comprising:
- a flash memory that transceives data through a flash bus group, a bus width (FW) of the flash bus group being greater than a bus width (HW) of the host bus group, where the bus width represents the number of bus lines that transceive data in parallel in response to a same clock signal;
- and
- a flash interface that controls a data transmission operation between the flash bus group and the host bus group,
- wherein the flash interface includes first through n'th flash input buffers that transfer data to the host bus group in stages in response to first through n'th transfer control clock signals, where n≧2, and
- wherein an i'th flash input buffer, where 2≦i≦n, provides data through i'th input-buffer bus groups in number of at least Ni, wherein a bus width (IBWi) of each of the i'th input-buffer bus groups is wider than a bus width (IBWi−1) of each of an (i−1)'th input-buffer bus groups, wherein a period (Ti) of an i'th transfer control clock signal is longer than a period (Ti−1) of an (i−1)'th transfer control clock signal, and wherein Ni is obtained by dividing the FW by the IBW.
A flash memory data storage apparatus that transceives data with an external system through a host bus group in parallel, comprising:
- a flash memory that transceives data through a flash bus group, a bus width (FW) of the flash bus group being greater than a bus width (HW) of the host bus group, where the bus width represents the number of bus lines that transceive data in parallel in response to a same clock signal;
- a buffer memory that temporarily stores transferred data;
- a host interface that controls data transmission between the host bus group and the buffer memory;
- and
- a flash interface that controls data transmission between the flash bus group and the buffer memory,
- wherein the flash interface includes first through n'th flash input buffers that transfer data to the host bus group in stages in response to first through n'th transfer control clock signals, where n≧2, and
- wherein an i'th flash input buffer, where 2≦i≦n, provides data through i'th input-buffer bus groups in number of at least Ni, wherein a bus width (IBWi) of each of the i'th input-buffer bus groups is wider than a bus width (IBWi−1) of each of an (i−1)'th input-buffer bus groups, wherein a period (Ti) of an i'th transfer control clock signal is longer than a period (Ti−1) of an (i−1)'th transfer control clock signal, and wherein Ni is obtained by dividing the FW by the IBW.
The flash memory data storage apparatus as set forth in 10, wherein the buffer memory comprises:
- first and second temporary storage units that each transceive data, which is composed of a bus width of the host bus group, with the host interface and the flash interface;
- and
- a buffering multiplexer that provides data of the host bus group from the host interface for an alternative one of the first and second temporary storage units, and that provides data from the first and second temporary storage units for an alternative one of the host interface and the flash interface.
Dependencies are inferred from the claim text.