Methods and systems for a reference clock
AssigneeHewlett-Packard Development Company, L.P.
InventorsRichard Lin, Jeffrey Jeansonne, Walter Fry
Life of this patent
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Abstract
In at least some embodiments, a method comprises receiving an external card detection signal that indicates that a hot-pluggable card is coupled to a computer system and activating at least one reference clock signal of a scalable reference clock platform based on the external card detection signal. The method further comprises synchronizing clock signals embedded in data packets transmitted between the hot-pluggable card and the computer system with another clock signal based on the at least one reference clock signal.
Claims25
A method, comprising:
- receiving an external card detection signal that indicates that a hot-pluggable card is coupled to a computer system;
- activating at least one reference clock signal of a scalable reference clock platform based on the external card detection signal;
- and
- synchronizing clock signals embedded in data packets transmitted between the hot-pluggable card and the computer system with another clock signal based on the at least one reference clock signal.
A method, comprising:
- configuring a reference clock unit for use with an external card detection signal by reducing a predetermined scalability associated with a reference clock architecture associated with the reference clock unit;
- and
- configuring the reference clock unit to activate a reference clock signal output based on the external card detection signal.
A system, comprising:
- a processor;
- a chipset coupled to the processor;
- and
- a reference clock unit coupled to the chipset and configured to output a scalable number of reference clock signals for synchronizing clock signals embedded in data packets with another clock signal,
- wherein the reference clock unit is configured to activate at least one of the reference clock signals based on an external card detection signal, said external card detection signal identifying when an external card is coupled to the system.
A reference clock unit, comprising:
- a clock generator configured to output a scalable number of reference clock signals, wherein the scalable number of reference clock signals is less than a predetermined maximum number of reference clock signals associated with the reference clock unit's platform;
- and
- clock control logic configured to assert an activation signal that causes the clock generator to activate at least one of the reference clock signals based on an external card detection signal.
Dependencies are inferred from the claim text.