US 2006/0136640 A1 · Apparatus and method for hardware semaphore

Abstract

A device and method for hardware semaphore is provided to be used in a multi-processor system. The device for hardware semaphore comprises a plurality of semaphores, a semaphore module register set, a control logic unit, a bus interface unit, and an interrupt generation unit. According to the invention, a single read operation of a memory location can allocate or acquire a semaphore, the hardware control logic circuit atomically execute the test and set operations. A hardware semaphore itself is considered as a shared resource. The multi-processor system can use a single read operation to request for the allocation of a specific or a random semaphore. The multi-processor system can also use a single read operation to request for the acquisition of a specific semaphore. The hardware semaphore device sets up interrupt signals to notify the processors in the system about the release of a semaphore which the processors fail to acquire.

Claims17

Dependent claims

A hardware semaphore device applicable to a multi-processor system having a bus matrix to independently read/write said hardware semaphore device, said hardware semaphore device comprising:

a plurality of semaphores, each said semaphore being arranged to manage a shared resource;
a semaphore module register set, for storing allocation information of said semaphore;
a control logic unit, electrically connected to said semaphores and said semaphore module register set respectively;
a bus interface unit, having two ends, with one said end connecting to said control logic unit, and the other said end connecting to each said processor through said bus matrix;
and
an interrupt generation unit, having two ends, with one said end connecting to said control logic unit, and the other said end connecting to each said processor through at least an interrupt signal line.

3 more elements

A method for realizing a hardware semaphore device, applicable to a multi-processor system, said hardware semaphore device comprising a plurality of semaphores and a semaphore module register set, each said semaphore further comprising a remaining resource number register, a initial resource number register, a waiting list register, a set waiting register, said semaphore module register set further comprising a random allocation register, an interrupted processor list register, and a plurality of allocation registers, in the initialization stage of said system, said system allocating at least a said semaphore to connect to and manage at least a shared resource on said system, any said processor having to acquire said semaphore before using said shared resource, and releasing said semaphore after using said shared resource, and freeing corresponding semaphore when said shared resource no longer required to be managed.

Dependencies are inferred from the claim text.

Apparatus and method for hardware semaphore

Life of this patent

Apparatus and method for hardware semaphore

Life of this patent

Abstract

Claims17