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US 2006/0136619 A1Published application
Data integrity processing and protection techniques
AssigneeIntel Corporation
InventorsSamantha Edirisooriya, Gregory Tse, Joseph Murray
Life of this patent
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Abstract
Techniques to accelerate block guard processing of data by use of block guard units in a path between a source memory device and an originator of a data transfer request. The block guard unit may intercept the data transfer request and data transferred in response to the data transfer request. The block guard unit may utilize a cache to store information useful to verify block guards associated with the data.
Claims21
A method comprising:
- storing at least one context in a cache;
- intercepting an access request transmitted to a source memory device;
- intercepting data transferred by the source memory device in response to the access request;
- selectively retrieving a context associated with the access request from a context cache based on availability of the context in the context cache;
- forming a block guard based on the associated context;
- selectively processing a block guard associated with the data based in part on the formed block guard;
- and
- transferring the data to a destination memory device.
5 more elements
An apparatus comprising:
- a block guard unit to intercept an access request transmitted to a source memory device and to intercept a data stream transferred by the source memory device in response to processing of the access request, wherein the block guard unit comprises:
- a cache to store at least one context;
- a control logic to determine whether a context associated with the access request is stored in the cache and to form a block guard based on the context provided by the cache;
- a lane shifter to selectively shift the first valid byte of the data stream to a zero byte lane among data lanes;
- a block guard computer to receive the data stream from the lane shifter and to selectively process a block guard associated with the data stream based in part on the formed block guard;
- and
- a multiplexer to selectively transfer the data stream and the formed block guard.
4 more elements
A system comprising:
- a host system comprising a processor, a memory device, and an intercommunication device;
- a local memory;
- a storage device communicatively coupled to receive information from the local memory and provide information to the local memory;
- an I/O system communicatively coupled to the intercommunication device and to provide information transfer between the local memory and the host system, wherein the I/O system includes:
- an I/O processor to initiate and sending of access requests to transfer information;
- and
- a block guard unit to intercept an access request transmitted to a source memory device and to intercept a data stream transferred by the source memory device in response to processing of the access request, wherein the block guard unit comprises:
- a cache to store at least one context;
- a control logic to determine whether a context associated with the access request is stored in the cache and to form a block guard based on the context provided by the cache;
- a lane shifter to selectively shift the first valid byte of the data stream to a zero byte lane among data lanes;
- a block guard computer to receive the data stream from the lane shifter and to selectively process a block guard associated with the data stream based in part on the formed block guard;
- and
- a multiplexer to selectively transfer the data stream and the formed block guard.
10 more elements
Dependencies are inferred from the claim text.