System and method for control registers accessed via private operations
OwnerJeffrey Gilbert, Harris Joyceinventors
Life of this patent
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Abstract
A system and method for accessing control registers in a computer system is described. In one embodiment, a control register is given an address which is outside the normal input/output addressable range. Additionally, this control register may be physically located in system circuits separate from the processor functional circuitry. Such a control register may not be accessible via normal user input/output instructions. Special microcode may be used to access these control registers. The special microcode may be executed by special system events. These special events may include loading a microcode patch, or by entering a special debug mode, or by test access using a test access port.
Claims51
An apparatus, comprising:
- logic to perform selected chipset functions;
- a bus interface to couple with a processor;
- and
- a control register accessed by an address outside of an input/output address space of said processor.
A processor, comprising:
- a first logic to execute an instruction set under control of a first microcode set;
- a physical register to contain an address not included in an input/output address space of said instruction set;
- and
- a second logic to access a control register using said address.
A system, comprising:
- a processor including a first logic to execute an instruction set under control of a first microcode set, and a physical register to contain an address not included in an input/output address space of said instruction set;
- and
- a module including a second logic to perform selected chipset functions, an interface to couple said module with said processor, and a control register accessed by said address.
A method, comprising:
- placing an address of a control register into a physical register of a processor, where said address is not included in an input/output address space of an instruction set under control of a first microcode set;
- and
- issuing said address from said physical register to said control register under control of a second microcode set.
An apparatus, comprising:
- means for placing an address of a control register into a physical register of a processor, where said address is not included in an input/output address space of an instruction set under control of a first microcode set;
- and
- means for issuing said address from said physical register to said control register under control of a second microcode set.
A computer-readable media containing software code that, when executed by a processor, performs the process comprising:
- placing an address of a control register into a physical register of a processor, where said address is not included in an input/output address space of an instruction set under control of a first microcode set;
- and
- issuing said address from said physical register to said control register under control of a second microcode set.
Dependencies are inferred from the claim text.