Enhanced fused multiply-add operation
AssigneeIntel Corporation
InventorsPing Tang, David Donofrio
Life of this patent
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AssigneeIntel Corporation
InventorsPing Tang, David Donofrio
Estimating the term…
An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate S1, where S1 is the sum of an integer k, the exponent of a floating point value A, and the exponent of a floating point value B. The exponent unit also includes a comparator to generate E1, where E1 is the greater of S1 and the exponent of a floating point value C. The apparatus also includes a partial multiplier, a shifter, and a second adder. The partial multiplier generates the partial products of the mantissas of A and B. The shifter aligns the partial products and the mantissa of C, based on E1. The second adder adds the aligned partial products and the mantissa of C. The apparatus is able to generate not only (A*B+C), but is enhanced to also be able to generate (2k*A*B+C) and the closest integer to (2k*A*B) in two's complement or floating point format.
An apparatus comprising:
The apparatus of claim I further comprising a multiplexer to set C to a constant in response to a control signal.
An apparatus comprising:
A method comprising:
A method comprising:
A system comprising:
A system comprising:
Dependencies are inferred from the claim text.