Data processing device with microprocessor and with additional arithmetic unit and associated method
AssigneeKoninklijke Philips Electronics N.V.
InventorsThomas Behling, Ralf Malzahn
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Abstract
In order to further develop a data processing device (100; 100′) having at least one microprocessor (90) and having at least one additional arithmetic unit (40) as well as a method of performing at least one particular defined calculation by means of the data processing device (100; 100′) in such a way that a plurality of calculations may be performed in sequence without any intervention by the microprocessor (90), it is proposed that the registers be loadable from at least one in particular peripheral memory (10), for example from at least one R[andom]A[ccess]M[emory], from at least one R[ead]O[nly]M[emory] or from at least one E[lectrically] E[rasable] P[rogrammable] R[ead]O[nly]M[emory.
Claims10
A data processing device having at least one microprocessor and having at least one additional arithmetic unit for performing at least one particular defined calculation, the arithmetic unit being coupled to the microprocessor via a number of registers, of which first registers are provided for controlling the data transfer and second registers are provided for transmitting commands, characterized in that the registers may be loaded from at least one particularly peripheral memory, for example
- from at least one R[andom]A[ccess]M[emory],
- from at least one R[ead]O[nly]M[emory] or
- from at least one E[lectrically] E[rasable] P[rogrammable] R[ead] O[nly] M[emory].
A method of performing at least one particular defined calculation by means of at least one data processing device having at least one microprocessor and having at least one additional arithmetic unit, characterized by the following method steps:
- (i) initialization of at least one address register and at least one counting register by the microprocessors;
- (ii) starting of the calculation by assertion of at least one control bit;
- (iii) copying or loading of data beginning at the start address from at least one in particular peripheral memory into at least one set of temporary registers;
- (iv) incrementation of the address register with each access to the memory;
- (v) establishing whether the set of temporary registers is complete:
- (v.a) if the set of temporary registers is complete (+), proceeding to method step (vi);
- (v.b) if the set of temporary registers is incomplete (−), proceeding to method step (iii);
- (vi) establishing whether the arithmetic unit is active:
- (vi.a) if the arithmetic unit is active (+), proceeding to method step (vi);
- (vi.b) if the arithmetic unit is inactive (−), proceeding to method step (vii);
- (vii) copying or transferal of data from the set of temporary registers into at least one set of main registers;
- (viii) decrementation of the counting register;
- (ix) starting of the calculation in the arithmetic unit;
- (x) establishing whether the counting register has been decremented to zero:
- (x.a) if the counting register has been decremented to zero (+), proceeding to method step (xi);
- (x.b) if the counting register has not been decremented to zero (−), proceeding to method step (iii);
- (xi) termination.
Dependencies are inferred from the claim text.