Leading zero counter for binary data alignment
AssigneeMathStar, Inc.
InventorFuk Ng
Life of this patent
Estimating the term…
Abstract
A method and apparatus are provided for aligning data in a binary word. A coded address is provided for each bit of the binary word. Each coded address is modified as a function of a logic state of the respective bit of the binary word to produce respective modified addresses. A shift control word is generated based on bit positions at which the modified addresses have a predetermined logic state. Bits in the binary word are shifted as a function of the shift control word to produce an aligned binary word.
Claims26
A method of aligning data in a binary word, the method comprising:
- (a) providing a coded address for each bit of the binary word;
- (b) modifying each coded address as a function of a logic state of the respective bit of the binary word to produce respective modified addresses;
- (c) generating a shift control word based on bit positions at which the modified addresses have a predetermined logic state;
- and
- (d) shifting bits in the binary word as a function of the shift control word to produce an aligned binary word.
A data alignment circuit comprising:
- a binary word input;
- a coded address for each bit of the binary word input;
- a first logic circuit, which modifies each coded address as a function of a logic state of the respective bit of the binary word input to produce respective modified addresses;
- a second logic circuit, which generates a shift control word based on bit positions at which the modified addresses have a predetermined logic state;
- and
- a shift circuit, which shifts bits in the binary word input as a function of the shift control word to produce an aligned binary word output.
A data alignment circuit comprising:
- a binary word input;
- a thermometer-coded address for each bit of the binary word input;
- means for modifying each thermometer-coded address as a function of a logic state of the respective bit of the binary word input to produce respective modified addresses;
- means for generating a shift control word based on bit positions at which the modified addresses have a predetermined logic state;
- and
- means for shifting bits in the binary word input as a function of the shift control word to produce an aligned binary word output.
A method of generating a leading zero count, the method comprising:
- receiving a binary word;
- and
- generating a count of leading zeros in the binary word with a substantially constant delay regardless of a number of bits in the binary word, except for changes in loading delay caused by changes in the number of bits in the binary word.
Dependencies are inferred from the claim text.