Method of evaluating system performance
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorKohsaku Shibata
Life of this patent
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Abstract
The system performance evaluation method of the present invention confirms the existence of the occurrence of a memory access penalty for each cycle (S101) and executes a CPU model only when a memory access penalty has not occurred (S202).
Claims6
A system performance evaluation method for evaluating a performance of a system comprising at least one CPU and memory hierarchy, comprising:
- a CPU simulation step of executing a simulation of the CPU;
- a memory simulation step of executing a simulation of the memory hierarchy;
- a system simulation step of executing the CPU simulation step and the memory simulation step in parallel;
- a CPU performance measurement step of measuring the performance of the CPU from which an effect of the memory hierarchy is removed;
- and
- a system performance measurement step of measuring a performance deterioration of the system caused by the effect of the memory hierarchy.
A system performance evaluation method comprising, as a system simulation for evaluating a performance of a system comprising at least one CPU and memory hierarchy, a step of executing a calculation in number of instruction execution cycles on the CPU when an effect of the memory hierarchy is removed, said method comprising:
- an instruction cache hit rate judgment step of judging, in accordance with a hit rate value of an instruction cache memory, simulation errors in results of calculation in number of instruction execution cycles on the CPU when an effect of the memory hierarchy is reflected in the calculation results, with respect to the calculation results when the effect of the memory hierarchy is removed;
- and
- an error display step of displaying the simulation error based on the results of the instruction cache hit rate judgment step.
A system performance evaluation method comprising, as a system simulation for evaluating a performance of a system comprising at least one CPU and memory hierarchy, a step of executing a calculation in number of instruction execution cycles on the CPU when an effect of the memory hierarchy is removed, said method comprising:
- a memory access penalty judgment step of judging, in accordance with a memory access penalty value, simulation errors in results of calculation in number of instruction execution cycles on the CPU when an effect of the memory hierarchy is reflected in the calculation results, with respect to the calculation results when the effect of the memory hierarchy is removed;
- and
- an error display step of displaying the simulation error based on the results of the instruction cache hit rate judgment step.
Dependencies are inferred from the claim text.