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US 2006/0134898 A1Published application
Semiconductor damascene trench and methods thereof
OwnerTodd Abbottinventor
Life of this patent
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Abstract
A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating the local interconnect to gate contact resistance. Further, the present invention provides flexible layout of active area to form small memory cells based upon the damascene gate and local interconnect structure. As such, the present invention is particularly suited for the fabrication of SRAM memory devices.
Claims20
A method of fabricating a semiconductor device comprising:
- forming a first dielectric layer over said base substrate;
- etching through said first dielectric layer to said base substrate to form a damascene trench in said first dielectric layer, said damascene trench having a gate area and a local interconnect area;
- growing an oxide layer on said base substrate, said oxide layer within said gate area of said damascene trench defining a gate oxide layer;
- forming a patterned mask over said semiconductor device, said patterned mask arranged to expose at least a portion of said oxide layer within said local interconnect area;
- etching away the exposed portion of said oxide layer within said damascene trench;
- providing at least one contact implant within a plug area in said base substrate, wherein said plug area is located at least partially beneath and in contact with said damascene local interconnect structure;
- stripping said patterned mask from said semiconductor device;
- depositing a conductive layer comprising a conductive material over said device such that said conductive material fills said damascene trench;
- removing said first dielectric layer to define a damascene gate structure and a damascene local interconnect structure.
6 more elements
A method of fabricating a semiconductor device comprising:
- forming a first dielectric layer over said base substrate;
- etching through said first dielectric layer to said base substrate to form a damascene trench in said first dielectric layer, said damascene trench having a gate area and a local interconnect area;
- growing an oxide layer on said base substrate, said oxide layer within said gate area of said damascene trench defining a gate oxide layer;
- forming a patterned mask over said semiconductor device, said patterned mask arranged to expose at least a portion of said oxide layer within said local interconnect area;
- etching away the exposed portion of said oxide layer within said damascene trench;
- providing at least one contact implant within a plug area in said base substrate, wherein said plug area is located at least partially beneath and in contact with said damascene local interconnect structure;
- stripping said patterned mask from said semiconductor device;
- depositing a conductive layer comprising a conductive material over said device such that said conductive material fills said damascene trench, wherein said conductive material comprises a polysilicon material;
- removing said first dielectric layer to define a damascene gate structure and a damascene local interconnect structure.
6 more elements
A method of fabricating a semiconductor device comprising:
- forming a first dielectric layer over said base substrate;
- etching through said first dielectric layer to said base substrate to form a damascene trench in said first dielectric layer, said damascene trench having a gate area and a local interconnect area;
- growing an oxide layer on said base substrate, said oxide layer within said gate area of said damascene trench defining a gate oxide layer;
- forming a patterned mask over said semiconductor device, said patterned mask arranged to expose at least a portion of said oxide layer within said local interconnect area;
- etching away the exposed portion of said oxide layer within said damascene trench;
- providing at least one contact implant within a plug area in said base substrate, wherein said plug area is located at least partially beneath and in contact with said damascene local interconnect structure;
- stripping said patterned mask from said semiconductor device;
- depositing a conductive layer comprising a conductive material over said device such that said conductive material fills said damascene trench;
- removing said first dielectric layer to define a damascene gate structure and a damascene local interconnect structure;
- depositing a spacer layer over said device;
- and
- shaping said spacer layer to form spacers against the vertical walls of said damascene gate structure and said damascene interconnect structure.
9 more elements
Dependencies are inferred from the claim text.