# US 2006/0134894 A1 · Method of manufacturing polycrystalline Si film and manufacturing stacked transistor using the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2006/0134894 A1
- Document ID: US20060134894A1
- Status: Published application
- Kind: A1
- Application number: 11/283,874
- Filed: 2005-11-22
- Published: 2006-06-22
- Earliest claimed: 2004-12-17
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Huaxiang Yin; Takashi Noguchi; Wenxu Xianyu; Kyung-bae Park
- Web page: https://patentgrep.com/patent/US20060134894A1

## CPC

- H10D 86/01: Manufacture or treatment
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/0227: {using structural arrangements to control crystal growth, e.g. placement of grain filters}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/2922: {being non-crystalline insulating materials, e.g. glass or polymers}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3241: {being conductive materials}
- H10P 14/3244: {Layer structure}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3808: {using laser beams}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed, forming an interconnection metal line separated from the gate, forming an insulating layer that covers the transistor and the interconnection metal line, forming an amorphous silicon layer on the insulating layer; and annealing the amorphous silicon layer.

## Claims

### Claim 1

A method of manufacturing a polycrystalline Si film, the method comprising:
preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed;
forming an interconnection metal line at a predetermined distance from the gate;
forming an insulating layer that covers the transistor and the interconnection metal line;
forming an amorphous silicon layer on the insulating layer; and
annealing the amorphous silicon layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the annealing of the amorphous silicon layer forms a polycrystalline Si film crystallized in lateral directions on the insulating layer between the transistor and the interconnection metal line by annealing the amorphous silicon layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the amorphous silicon layer is annealed using a laser beam.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming of the insulating layer that covers the transistor and the interconnection metal line further includes planarizing the insulating layer after forming the insulating layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the insulating substrate is a glass substrate or a plastic substrate.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gate and the interconnection metal line are each formed of a material having high thermal conductivity.

### Claim 7 (depends on 6)

The method of claim 6, wherein the interconnection metal line is formed of at least one metal selected from the group consisting of Al, Cr, Cu, and Mo.

### Claim 8 (depends on 1)

The method of claim 1, wherein the interconnection metal line is formed parallel to the gate.

### Claim 9 (depends on 1)

The method of claim 1, wherein the preparing of an insulating substrate on which a transistor is formed includes:
preparing an insulating substrate; and
forming a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed.

### Claim 10

A method of manufacturing a stacked transistor, the method comprising:
preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed;
forming an interconnection metal line at a predetermined distance from the gate;
forming an insulating layer that covers the transistor and the interconnection metal line;
forming an amorphous silicon layer on the insulating layer;
forming a polycrystalline Si film crystallized in lateral directions on the insulating layer between the transistor and the interconnection metal line by annealing the amorphous silicon layer; and
forming a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, using the polycrystalline Si film.

### Claim 11 (depends on 10)

The method of claim 10, wherein the amorphous silicon layer is annealed using a laser beam.

### Claim 12 (depends on 10)

The method of claim 10, wherein the forming of the insulating layer that covers the transistor and the interconnection metal line further includes planarizing the insulating layer after forming the insulating layer.

### Claim 13 (depends on 10)

The method of claim 10, wherein the insulating substrate is a glass substrate or a plastic substrate.

### Claim 14 (depends on 10)

The method of claim 10, wherein the gate and the interconnection metal line are each formed of a material having high thermal conductivity.

### Claim 15 (depends on 14)

The method of claim 14, wherein the interconnection metal line is formed of at least one metal selected from the group consisting of Al, Cr, Cu, and Mo.

### Claim 16 (depends on 10)

The method of claim 10, wherein the interconnection metal line is formed parallel to the gate.

### Claim 17 (depends on 10)

The method of claim 10, wherein the preparing of an insulating substrate on which a transistor is formed includes:
preparing an insulating substrate; and
forming a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed.