Charge-trapping memory device and method of production

A method for producing charge-trapping memory devices, the method comprising:

• providing a semiconductor body having a main surface;
• arranging a gate electrode having opposite lateral edges above said main surface and forming an electrically insulating gate dielectric between said gate electrode and the semiconductor body;
• etching said gate dielectric to form recesses at opposite lateral edges of said gate electrode;
• applying a memory layer of dielectric material suitable for charge-trapping;
• removing said memory layer except for limited charge-trapping regions that are located in said recesses and that extend from said gate dielectric for a distance that is short of said lateral edges such that the outer limits of said charge-trapping regions are recessed with respect to said lateral edges;
• and
• forming doped source/drain regions by an introduction of a dopant into the semiconductor body at said main surface in a self-aligned fashion with respect to said charge-trapping regions and wherein said introduction of said dopant comprises a process selected from the group consisting of gas phase doping, deposition of a doped layer followed by a thermal diffusion of the dopant, and plasma doping at low energy.

A method for producing charge-trapping memory devices, the method comprising:

• providing a semiconductor body having a main surface;
• arranging a gate electrode having opposite lateral edges above said main surface and forming an electrically insulating gate dielectric between said gate electrode and the semiconductor body;
• etching said gate dielectric to form recesses at opposite lateral edges of said gate electrode;
• applying a memory layer of Al2O3 dielectric material suitable for charge-trapping by means of atomic layer deposition form alternating trimethylaluminum and water;
• removing said memory layer except for limited charge-trapping regions that are located at in said recesses and that extend from by said gate dielectric for a distance that is short of said lateral edges such that the outer limits of said charge trapping regions are recessed with respect to said lateral edges;
• and
• forming doped source/drain regions by an introduction of a dopant into the semiconductor body at said main surface in a self-aligned fashion with respect to said charge-trapping regions and wherein said introduction of said dopant comprises a process selected from the group consisting of gas phase doping, deposition of a doped layer followed by a thermal diffusion of the dopant, and plasma doping at low energy.

A method for producing charge-trapping memory devices, the method comprising:

• providing a semiconductor body having a main surface;
• arranging a gate electrode having opposite lateral edges above said main surface and forming an electrically insulating gate dielectric between said gate electrode and the semiconductor body;
• etching said gate dielectric to form recesses at opposite lateral edges of said gate electrode;
• applying confinement layers of dielectric material into said recesses to improve retention of stored charge carriers within charge trapping region;
• applying a memory layer of dielectric material suitable for charge-trapping after applying said confinement layers;
• removing said memory layer except for limited charge-trapping regions that are located in said recesses and that extend from by said gate dielectric for a distance that is short of said lateral edges such that the outer limits of said charge trapping regions are recessed with respect to said lateral edges;
• and
• forming doped source/drain regions by an introduction of a dopant into the semiconductor body at said main surface in a self-aligned fashion with respect to said charge-trapping regions and wherein said introduction of said dopant comprises a process selected from the group consisting of gas phase doping, deposition of a doped layer followed by a thermal diffusion of the dopant, and plasma doping at low energy.

A method for producing charge-trapping memory devices, the method comprising:

• providing a semiconductor body having a main surface;
• arranging a gate electrode having opposite lateral edges above said main surface and forming an electrically insulating gate dielectric between said gate electrode and the semiconductor body;
• etching said gate dielectric to form recesses at opposite lateral edges of said gate electrode;
• applying a memory layer of dielectric material suitable for charge-trapping;
• removing said memory layer except for limited charge-trapping regions that are located X in said recesses and that extend from by said gate dielectric for a distance that is short of said lateral edges such that the outer limits of said charge trapping regions are recessed with respect to said lateral edges, said charge trapping region having a dimension in a longitudinal direction along a line connecting said source/drain regions no greater than 20 nm;
• and
• forming doped source/drain regions by an introduction of a dopant into the semiconductor body at said main surface in a self-aligned fashion with respect to said charge-trapping regions and wherein said introduction of said dopant comprises of a process selected from the group consisting of gas phase doping, deposition of a doped layer followed by a thermal diffusion of the dopant, and plasma doping at low energy.

A method for producing charge-trapping memory devices, the method comprising:

• providing a semiconductor body having a main surface;
• arranging a gate electrode having opposite lateral edges above said main surface and forming an electrically insulating gate dielectric between said gate electrode and the semiconductor body;
• etching said gate dielectric to form recesses at opposite lateral edges of said gate electrode;
• applying a memory layer of Al2O3 dielectric material suitable for charge-trapping by means of atomic layer deposition (ALD);
• removing said memory layer except for limited charge-trapping regions that are located at in said recesses and that extend from said gate dielectric for a distance that is short of said lateral edges such that the outer limits of said charge trapping regions are recessed with respect to said lateral edges;
• and
• forming doped source/drain regions by an introduction of a dopant into the semiconductor body at said main surface in, a self-aligned fashion with respect to said charge-trapping regions.

A method for producing charge-trapping memory devices, comprising:

• providing a semiconductor body having a main surface;
• forming an electrically insulating gate dielectric over and in contact with said main surface of said semiconductor body;
• forming a gate electrode having opposite lateral edges over and in contact with said gate dielectric;
• etching all of said gate dielectric between said gate electrode and the main surface of the semiconductor body for a selected distance extending from opposite lateral edges of said gate electrode to form recesses on each side of said gate electrode and an intermediate portion of said electrically insulating gate dielectric;
• partially filling said recesses with a memory layer of dielectric material extending from said get dielectric to outer limits short of said lateral edges such that said dielectric material is recessed with respect to said lateral edges, said dielectric material forming regions for charge trapping;
• forming doped source/drain regions by an introduction of a dopant into the semiconductor body at said main surface in a self aligned fashion with respect to said charge-trapping regions.