Double gate field effect transistor and method of manufacturing the same

A method of manufacturing a double gate field effect transistor, comprising:

• forming a pad insulating layer on a semiconductor substrate;
• forming a first hard mask layer pattern on the pad insulating layer;
• forming a pad insulating layer pattern and fins by sequentially etching the pad insulating layer and the substrate using the first hard mask layer pattern as a etch mask;
• forming an non-channel gate oxide film on the substrate in areas where no fins are formed;
• forming a second hard mask layer pattern that covers the fins and a portion of the non-channel gate oxide film on the substrate;
• forming trenches on the substrate by etching the non-channel gate oxide film and the substrate using the second hard mask layer pattern as an etch mask;
• forming device isolation insulating film patterns in the trenches;
• forming channel gate oxide films on the first side face and the second side face of the fins;
• and
• forming a gate line that surrounds the channel gate oxide film and the pad insulating layer pattern.

A double gate field effect transistor comprising:

• a silicon substrate having an active region defined by a device isolation trench region;
• a fin protruding from the active region, the fin having an upper face, a first side face, and a second side face;
• a source region and a drain region separated from each other by a channel region, the fin spanning the channel region from the source region to the drain region;
• a first and a second channel gate oxide film formed on the first side face and the second side face, respectively;
• a pad insulating film pattern formed on the upper face;
• a device isolation insulating film pattern that fills the device isolation trench region;
• a non-channel gate oxide film formed on the substrate in the active region where the fin is not present;
• and
• a gate line formed on the gate oxide films, the pad insulating film pattern, and the non-channel gate oxide film.