US 2006/0134865 A1 · Method of manufacturing a semiconductor device

Abstract

According to the present invention, a method of manufacturing a semiconductor device which comprises a matrix of memory cells of the floating gate type is provided in which the silicon nitride layer is deposited as an etching stop layer on a control gate electrode for bottom borderless contact process with the threshold voltage of transistor arrangements being controlled not to change so that the productivity can remain not declined. In particular, the silicon nitride layer (115) is deposited as an etching stop layer on the control gate electrode (105) for bottom borderless contact process so that the concentration of hydrogen (H2) therein stays in a range from 1.5×1021 to 2.6×1021 atoms/cm3. Also, the silicon nitride layer (115) is deposited at a temperature of not higher than 700° C. by a low pressure CVD technique.

Claims11

Dependent claims

A method of manufacturing a semiconductor device which comprises a matrix of memory cells, each memory cell including source and drain regions provided on a semiconductor substrate and a layer construction of a gate insulating layer, a floating gate, another insulating layer, and a control gate deposited on a channel region located between the source and drain regions, wherein

the concentration of hydrogen in a silicon nitride layer deposited on the control gate electrode as the etching stop layer for bottom borderless contact process stays in a range from 1.5×1021 atoms/cm3 to 2.6×1021 atoms/cm3.

Dependencies are inferred from the claim text.

Facts

Application

11/303,583Filed 14 Dec 2005

Priority

JP 2004-36647317 Dec 2004

Published

22 Jun 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…

Method of manufacturing a semiconductor device

Life of this patent

Method of manufacturing a semiconductor device

Life of this patent

Abstract

Claims11