CMOS NVM bitcell and integrated circuit

A non-volatile memory (NVM) bitcell structure comprising:

• a first metal-insulator-metal (MIM) capacitor having a first capacitance value, the first MIM capacitor including a first top plate, a first bottom plate, and a first dielectric disposed in-between the first top plate and the first bottom plate;
• a second capacitor having a second capacitance value, the second capacitor including an element electrically coupled in common with an element of the first MIM capacitor and wherein the first capacitance value is greater than the second capacitance value;
• a substrate, wherein the first MIM capacitor is formed in an interlevel dielectric overlying the substrate;
• a MOS transistor having a source region and a drain region formed within an active region of the substrate, the MOS transistor further having a floating gate and a gate dielectric disposed between the floating gate and the active region, further wherein the first bottom plate is electrically coupled to the floating gate;
• and
• an erase structure, wherein the erase structure comprises an erase well formed within the substrate, a dielectric layer formed over a portion of the erase well, and an electrode formed overlying the dielectric layer, wherein the electrode is electrically coupled to the floating gate of the MOS transistor and wherein the electrode, dielectric, and erase well form the second capacitor of the NVM bitcell structure.