Method of manufacturing a SiC vertical MOSFET

A method of manufacturing a silicon carbide (SiC) vertical MOSFET, the method comprising:

• forming an SiC mask on a surface of a layer of SiC, the SiC mask having side surfaces substantially parallel to a normal to the surface of the layer of SiC;
• implanting first ions into the layer of SiC through the surface in a direction forming an angle not larger than 70° with the surface, using the SiC mask as an ion implantation mask, to produce a base region having a first conductivity type in the layer of SiC;
• and
• implanting second ions into the layer of SiC through the surface in a direction substantially parallel to the normal, using the SiC mask as an ion implantation mask to produce a source region having a second conductivity type, opposite the first conductivity type, within the base region, so that channel length of the base region, measured along the surface, is at least 0.3 microns.

A method of manufacturing a silicon carbide (SiC) vertical MOSFET, the method comprising:

• forming an SiO2 mask on a surface of a layer of SiC, the SiO2 mask having side surfaces forming substantially parallel to a normal to the surface of the layer of SiC;
• implanting first ions into the layer of SiC through the surface in a direction forming an angle not larger than 75° with the surface, using the SiO2 mask as an ion implantation mask, to produce a base region having a first conductivity type in the layer of SiC;
• and
• implanting second ions into the layer of SiC through the surface in a direction substantially parallel to the normal, using the SiO2 mask as an ion implantation mask to produce a source region having a second conductivity type, opposite the first conductivity type, within the base region, so that the base region has a thickness, relative to the source region, of at least 0.3 microns.