Vertically stacked field programmable nonvolatile memory and method of fabrication
AssigneeSanDisk 3D LLC
InventorsVivek Subramanian, James Cleeves
Life of this patent
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Abstract
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Claims10
A process for fabricating a cell in a 3-D semiconductor memory device comprising:
- forming a first conductor layer;
- forming a first semiconductor layer overlying the conductor layer;
- oxidizing at least a portion of the first semiconductor layer in a plasma to form an oxide layer thereon;
- forming a second semiconductor layer overlying the oxide layer;
- sequentially etching the second semiconductor layer, the oxide layer, the first semiconductor layer and the first conductor layer to form a line;
- forming a second conductor layer overlying the line;
- and
- sequentially etching the second conductor layer and the line to form a pillar of the 3-D semiconductor memory device, wherein the 3-D semiconductor memory device comprises a plurality of layers of memory cells stacked vertically above one another.
A process for fabricating a cell in a 3-D semiconductor memory device comprising:
- forming a first conductor layer;
- forming a first semiconductor layer overlying the first conductor layer;
- oxidizing at least a portion of the first semiconductor layer to form an oxide layer thereon;
- forming a second semiconductor layer overlying the oxide layer;
- sequentially etching the second semiconductor layer, the oxide layer, the first semiconductor layer, the first conductor layer to form a line;
- forming a second conductor layer overlying the first line;
- etching the second conductor layer to form a second line orthogonal to the first line and etching the first line to form a pillar;
- and
- forming edge regions on the pillar using a plasma oxidation process;
- wherein the 3-D semiconductor memory device comprises a plurality of layers of memory cells stacked vertically above one another.
Dependencies are inferred from the claim text.