Integrated circuit packaging using electrochemically fabricated structures
AssigneeMicrofabrica Inc.
InventorsAdam Cohen, Vacit Arat, Michael Lockard, Christopher Folk, Marvin Kilgo
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Abstract
Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material, or conductive material containing passages that allow the flow of fluid to maintain desired thermal properties of the packaged electronic components.
Claims30
A process for fabricating a packaged electronic component, comprising:
- providing a substrate having conductive vias;
- forming routing elements on the substrate which have first and second ends, where at least some of the first ends are connectable to a first electronic component and at least some of the second ends are electrically connected to vias on the substrate;
- and
- connecting the first electronic component to the at least some of the first ends.
A process for fabricating a packaged electronic component, comprising:
- providing a substrate having conductive vias;
- forming routing elements which have first and second ends, where at least some of the first ends are connectable to a first electronic component and at least some of the second ends are connectable to vias on the substrate;
- and
- electrically connecting the at least some of the second ends to the vias comprising a bonding operation;
- electrically connecting the first electronic component to the at least some of the first ends.
A process for fabricating a plurality of packaged electronic components, comprising:
- providing a substrate;
- forming routing elements on the substrate which have first and second ends, where at least some of the first ends are electrically connectable to a first electronic component and at least some of the second ends are electrically connectable to a second electronic component;
- attaching the first and second electronic components to the at least some of the first ends and second ends, respectively.
A process for fabricating a plurality of packaged electronic components, comprising:
- providing a substrate;
- forming routing elements which have first and second ends, where at least some of the first ends are electrically connectable to a first electronic component and at least some of the second ends are electrically connectable to a second electronic component;
- establishing a thermally conductive connection between the substrate and routing elements;
- and
- electrically connecting the first and second electronic components to the at least some of the first ends and second ends, respectively.
A fabrication process for fabricating a package for holding an electronic component, comprising:
- (a) forming and adhering a layer of material to a previously formed layer and/or to a substrate, wherein the layer comprises a desired pattern of at least one material;
- and
- (b) repeating the forming and adhering operation of (a) a plurality of times to build up a configuration of conductive interconnect elements, wherein the plurality of layers are adhered to one another and comprise at least one of (i) at least one structural material and at least one sacrificial material or (ii) at least two structural materials one of which is a conductor and one of which is a dielectric;
- and
- wherein at least one of the following is true:
- (1) the package comprises metal electrodeposited or electroless deposited on a layer-by-layer basis where the height of at least some layers is set by a planarization operation that planarizes an interconnect material and at least one other material;
- (2) the package comprises vias and traces that coexist on at least some layers;
- (3) the package comprises at least one more coaxial interconnects;
- (4) the package comprises interconnects having traces having at least two different widths;
- (5) the package comprises interconnects comprising vias that have at least two different widths;
- (6) the package comprises interconnects having trace thicknesses that are at least as thick as some planarized thicknesses of a dielectric material;
- (7) the package comprises interconnects having trace thicknesses that are at least as thick as the differential height between some interconnect traces;
- (8) the at least one layer of the package is formed using a process comprising:
- patterning a first material, applying a non-planar seed layer, electrodepositing a second material, and trimming off at least a portion of the deposited first material.
Dependencies are inferred from the claim text.