Shrinking key generator for parallel process
AssigneeElectronics and Telecommunications Research Institute
InventorsDong Kim, Young Kim, Dae Park, Jang Hong Yoon
Life of this patent
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Abstract
A parallel processing shrinking key generator is provided. The parallel processing shrinking key generator includes: a selection linear feedback shift register (LFSR); a source LFSR; a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR; an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal, and an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter.
Claims9
A parallel processing shrinking key generator having a selection linear feedback shift register (LFSR), a source LFSR and an output amount register, the parallel processing shrinking key generator comprising:
- a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR;
- an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal;
- and
- an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter.
Dependencies are inferred from the claim text.