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US 2006/0133559 A1Published application
Programmable fractional N phase locked loop architecture and method
OwnerKevin Glassinventor
Life of this patent
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Abstract
A fractional N phase locked loop (PLL) includes a programmable digital signal processor (DSP) to perform various processing functions within the PLL. In at least one embodiment, the programmable nature of the DSP allows programs to be modified and/or added to the PLL to support a variety of different applications.
Claims36
A fractional N phase locked loop comprising:
- a voltage controlled oscillator (VCO) to generate an output signal in response to an input control signal;
- a loop filter to generate said input control signal of said VCO;
- a multi-modulus prescaler to receive said output signal of said VCO and to divide a frequency of said output signal by a variable divisor value to generate a comparison signal;
- and
- a programmable digital signal processor (DSP) to compare a phase of said comparison signal to a phase of a reference signal and to generate an output signal based on said comparison.
2 more elements
A communication device comprising:
- a power amplifier to drive at least one antenna;
- and
- a fractional N phase locked loop comprising:
- a voltage controlled oscillator (VCO) to generate an output signal in response to an input control signal;
- a loop filter to generate said input control signal of said VCO;
- a multi-modulus prescaler to receive said output signal of said VCO and to divide a frequency of said output signal by a variable divisor value to generate a comparison signal;
- and
- a programmable digital signal processor (DSP) to compare a phase of said comparison signal to a phase of a reference signal and to generate an output signal based on said comparison.
5 more elements
A method comprising:
- comparing, within a digital signal processor (DSP), a phase of a comparison signal to a phase of a reference signal in a phase locked loop (PLL);
- and
- developing an input signal for a loop filter in said PLL, using said DSP, based on said comparison.
An article comprising a storage medium having instructions stored thereon that, when executed by a computing platform, operate to:
- compare a phase of a comparison signal to a phase of a reference signal in a phase locked loop (PLL);
- and
- develop an input signal for a loop filter in said PLL based on said comparison.
Dependencies are inferred from the claim text.