Mechanism to aid a phase interpolator in recovering a clock signal

A method, comprising:

• receiving a plurality of reference clock signals;
• maintaining a common mode of the plurality of reference clock signals by a common mode circuit, the common mode circuit including an alternating current (AC) capacitor and a common mode bias keeper circuit;
• generating interrelated control signals based on comparing the plurality of reference clocks to a received data signal;
• and
• outputting amplitude contributions from phases of the interrelated control signals.

A receiver, comprising:

• a local reference clock providing a plurality of clock phases;
• a clock and data recovery unit to receive a serial data signal from a transmitter;
• and
• a phase interpolator within the clock and data recovery unit, the phase interpolator including:
• an alternating current (AC) coupling capacitor;
• and
• a common mode bias keeper circuit coupled to the AC coupling capacitor,
• wherein the AC coupling capacitor and the common bias keeper circuit operate together to force the common mode of phase interpolator input signals to be the same.