US 2006/0133555 A1 · Clock generation circuit and method thereof

Abstract

The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK2 once and the clock signal CLK1 (Q−1) times and then to generate the clock signal CLK1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK1 once and the clock signal CLK2 (Q−1) times and then to generate the clock signal CLK2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B−C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.

Claims8

Dependent claims

A clock generation circuit for generating an output clock signal having a frequency freq between a frequency fref/A of a first divided clock signal and a frequency fref/(A+1) of a second divided clock signal on the basis of the first divided clock signal obtained by dividing a reference clock signal having a frequency fref by A and the second divided clock signal obtained by dividing the reference clock signal by (A+1), said clock generation circuit comprising:

dividing means for selectively generating the first divided clock signal and the second divided clock signal and for outputting the selected divided clock signal as the output clock signal;
and
correction means for controlling said dividing means so as to repeat C times the process of generating the second divided clock signal once and generating the first divided clock signal (Q−1) times if C<D and for controlling said dividing means so as to repeat D times the process of generating the first divided clock signal once and generating the second divided clock signal (Q−1) times if C>D,
where A, B, and C are natural numbers satisfying the following formula (1):
freq=fref/(A+C/B) (1);
and
where D=B−C, Q is the quotient of B/C for C<D, and Q is the quotient of B/D for C>D.

4 more elements

A clock generation method for generating an output clock signal having a frequency freq between a frequency fref/A of a first divided clock signal and a frequency fref/(A+1) of a second divided clock signal on the basis of the first divided clock signal obtained by dividing a reference clock signal having a frequency fref by A and the second divided clock signal obtained by dividing the reference clock signal by (A+1), said clock generation method comprising the steps of:

generating the second divided clock signal once if C<D;
generating the first divided clock signal (Q−1) times after generating the second divided clock signal;
repeating the steps of generating the second and first divided clock signals C times;
generating the first divided clock signal once if C>D;
generating the second divided clock signal (Q−1) times after generating the first divided clock signal;
and
repeating said steps of generating the first and second divided clock signals D times,
where A, B, and C are natural numbers satisfying the following formula (1):
freq=fref/(A+C/B) (1);
and
where D=B−C, Q is the quotient of B/C for C<D, and Q is the quotient of B/D for C>D.

8 more elements

Dependencies are inferred from the claim text.

Clock generation circuit and method thereof

Life of this patent

Clock generation circuit and method thereof

Life of this patent

Abstract

Claims8