Pleisiochronous repeater system and components thereof
AssigneeRambus Inc.
InventorsRobert Palmer, Thomas Greer, Stephen Tell
Life of this patent
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Abstract
A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.
Claims38
A receiver circuit comprising:
- a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal;
- and
- a divider circuit that generates, based at least in part upon the data clock signal, a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.
A transmitter circuit comprising:
- a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal;
- and
- a divider circuit for generating, based at least in part upon the data clock signal, a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.
A pleisiochronous repeater system comprising:
- a receiver that receives serial input data, converts the serial input data into parallel output data, and generates a receiver timing reference signal having a frequency that is not an integer divisor of a frequency of a reference clock signal from which a receiver data clock signal is generated;
- and
- a transmitter that receives the parallel output data, converts the received parallel output data into serial output data, and generates a transmitter timing reference signal having a frequency that is not an integer divisor of the frequency of the reference clock signal from which a transmitter data clock signal is generated.
A method for operating a receiver circuit, the method comprising:
- multiplying a reference clock signal by an integer multiple to generate a data clock signal;
- and
- generating, based at least in part upon the data clock signal, a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.
A method for operating a transmitter circuit, the method comprising:
- multiplying a reference clock signal by an integer multiple to generate a data clock signal;
- and
- generating, based at least in part upon the data clock signal, a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.
A method of operation in a pleisiochronous repeater system, the method comprising:
- receiving serial input data;
- converting the serial input data into parallel output data;
- generating a receiver timing reference signal having a frequency that is not an integer divisor of a frequency of a reference clock signal from which a receiver data clock signal is generated;
- receiving the parallel output data;
- converting the received parallel output data into serial output data;
- and
- generating a transmitter timing reference signal having a frequency that is not an integer divisor of the frequency of the reference clock signal from which a transmitter data clock signal is generated.
Dependencies are inferred from the claim text.