Memory having internal column counter for compression test mode

An internal column counter for a random access memory, the internal column counter comprising:

• a data valid counter configured to count data valid signals and provide an enable signal in response to a count equal to zero;
• a first column address latch configured to latch a column address in response to a read command;
• and
• a second column address latch configured to latch the column address passed from the first column address latch in response to the enable signal,
• wherein the second column address latch provides the column address for generating a compression register of expected data to compare to data read from a memory array in a compression test mode.

An internal column counter for a read sequence for a compression test mode of a dynamic random access memory, the internal column counter comprising:

• a data valid counter configured provide a most significant counter bit signal and an enable signal based on a count of data valid signals;
• a first latch configured to latch a column address in response to a read command;
• a tri-state buffer configured to be enabled in response to the enable signal;
• a second latch configured to receive the column address from the first latch through the tri-state buffer with the tri-state buffer enabled;
• and
• an XOR gate configured to receive the column address from the second latch and invert the column address in response to the most significant counter bit signal.

A dynamic random access memory comprising:

• an array of memory cells;
• and
• an internal column counter for a read sequence in a compression test mode, the internal column counter comprising:
• means to provide a first column address for generating a compression register of expected data to compare to data read from the array of memory cells in response to a first read command;
• means to latch a second column address in response to a second read command while the first read command is executing;
• and
• means to provide the second column address for generating the compression register of expected data to compare to data read from the array of memory cells in response to the second read command once execution of the first read command is completed.

A method for testing a memory in a compression test mode, the method comprising:

• providing a first column address for generating a compression register of expected data to compare to data read from an array of memory cells in response to a first read command;
• latching a second column address in response to a second read command while the first read command is executing;
• and
• providing the second column address for generating the compression register of expected data to compare to data read from the array of memory cells in response to the second read command once execution of the first read command is completed.

A method for testing a memory in a compression test mode, the method comprising:

• resetting a data valid count to zero;
• providing a first enable signal in response to the data valid count of zero;
• latching a first column address in a first latch in response to a first read command;
• latching the first column address in a second latch in response to the first enable signal to provide the first column address for generating a compression register of expected data to compare to data read from an array of memory cells in response to the first read command;
• incrementing the data valid count in response to a first data valid signal;
• and
• latching a second column address in the first latch in response to a second read command received before the first read command is fully executed.

A method for testing a memory in a compression test mode, the method comprising:

• resetting a data valid count to zero;
• providing a first enable signal in response to the data valid count of zero;
• enabling a tri-state buffer in response to the first enable signal;
• latching a first column address in a first latch in response to a first read command;
• latching the first column address in a second latch in response to the first column address passing through the ti-state buffer;
• passing the first column address in the second latch for generating a compression register of expected data to compare to first data read from a memory array in response to the first read command;
• incrementing the data valid count in response to a first data valid signal indicating the first data read from the memory array in response to the first read command is valid;
• inverting and passing the first column address in the second latch for generating a compression register of expected data compensated for the topology of the memory array to compare to second data read from the memory array in response to the first read command, and
• latching a second column address in the first latch in response to a second read command before the first read command is fully executed.