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US 2006/0133186 A1Published application
Memory access using multiple activated memory cell rows
AssigneeInfineon Technologies AG
InventorKlaus Hummler
Life of this patent
Estimating the term…
Abstract
For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common to activated rows and the selected column. At least one of the selected memory cells common to activated rows and the selected column is selectively accessed. The selecting and the selectively accessing are repeated to access memory cells common to activated rows and a plurality of selected columns.
Claims20
A method for providing burst access to memory comprising:
- activating a plurality of rows of memory cells in a memory bank;
- selecting a column of memory cells in the memory bank to select memory cells common to activated rows and the selected column;
- selectively accessing at least one of the selected memory cells common to activated rows and the selected column;
- and
- repeating the selecting and the selectively accessing to access memory cells common to activated rows and a plurality of selected columns.
2 more elements
An apparatus comprising:
- a memory bank having a plurality of memory cells;
- circuitry to activate a plurality of rows of memory cells in the memory bank;
- circuitry to select a column of memory cells in the memory bank to select memory cells common to activated rows and the selected column;
- circuitry to access selectively at least one of the selected memory cells common to activated rows and the selected column;
- and
- burst control circuitry to control the selection of a column of memory cells and the selective access to at least one of the selected memory cells common to activated rows and a selected column to access memory cells common to activated rows and a plurality of selected columns.
3 more elements
A system comprising:
- one or more processors;
- a memory controller;
- memory comprising one or more memory banks each having a plurality of memory cells;
- circuitry to activate a plurality of rows of memory cells in each of one or more of the memory banks;
- circuitry to select a memory bank, to select a column of memory cells in the selected memory bank to select memory cells common to activated rows and the selected column, and to access selectively at least one of the selected memory cells common to activated rows and the selected column;
- and
- burst control circuitry to control the selection of a memory bank, the selection of a column of memory cells, and the selective access to at least one of the selected memory cells common to activated rows and a selected column to access memory cells common to activated rows and a plurality of selected columns in each of at least one selected memory bank.
4 more elements
Dependencies are inferred from the claim text.