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US 2006/0133185 A1Published application
Memory array leakage reduction circuit and method
AssigneeIntel Corporation
InventorsJeffrey Miller, Mahadevamurty Nemani, James Conary
Life of this patent
Estimating the term…
Abstract
Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.
Claims27
A chip comprising:
- a memory array with word-line rows, each word-line row including:
- bit cells coupled to a word-line node and to a virtual ground node, the word-line node to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive, the virtual ground node to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode;
- and
- a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes, wherein current leakage in the bit cells and word-line driver circuit is reduced during the standby mode with the virtual ground node being at the elevated voltage.
1 more element
A chip comprising:
- a memory array having word-line rows including:
- bit cells coupled to a word-line node and a virtual ground node, the word-line node to be at an active word-line voltage when the row is active and an inactive word-line voltage when inactive, the virtual ground node to be at an operational ground level when the memory array is enabled and at an elevated, leakage reduction level when the memory array is in a standby mode;
- and
- a driver circuit coupled to the bit cells through the word-line to provide the active word-line voltage when activated, the driver circuit being operably powered when the memory array is enabled and underpowered for reducing current leakage when the memory array is in the standby mode.
1 more element
A system for a computer, comprising:
- (a) a microprocessor having a memory array with word-line rows each including:
- (i) bit cells coupled to a word-line node and to a virtual ground node, the word-line node to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive, the virtual ground node to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode, and (ii) a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes, wherein current leakage in the bit cells and word-line driver circuit is reduced during the standby mode with the virtual ground node being at the elevated voltage;
- and
- (b) a wireless interface component to be coupled to the microprocessor chip to establish a wireless link between the microprocessor and a device outside of the system.
1 more element
A memory array comprising:
- a virtual ground node common to the memory array, the virtual ground node to be operated at an operational ground when the memory array is enabled and at an elevated ground voltage when the array is in a standby mode;
- and
- word-line rows each having a word-line driver circuit operably coupled to a plurality of bit cells through the virtual ground node, the virtual ground node reducing leakage in the bit cells and word-line driver circuits when the array is in the standby mode.
Dependencies are inferred from the claim text.