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US 2006/0133183 A1Published application
Multi read port bit line
AssigneeIntel Corporation
InventorsSteven Hsu, Atul Maheshwari, Ram Krishnamurthy
Life of this patent
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Abstract
In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.
Claims28
A chip, comprising:
- (a) a bit line;
- (b) a plurality of bit cells each coupled to the bit line;
- and
- (c) a sense amplifier coupled to the bit line, said sense amplifier having first and second read ports and sensing at least four different impedance levels on the bit line to simultaneously read at least two of the bit cells and indicate their values at said first and second read ports.
1 more element
A chip, comprising:
- a register file circuit comprising:
- (i) a bit line having an impedance;
- (ii) bit cells coupled to the bit line;
- and
- (iii) a sense amplifier coupled to the bit line, said sense amplifier sensing at least four different impedance levels on the bit line to read at least two of the bit cells during a single read operation.
2 more elements
A method comprising:
- (a) providing in a register file circuit at least one bit line having an impedance;
- (b) coupling a plurality of bit cells to the at least one bit line, wherein each bit cell, when operated, adjusts the bit line impedance to indicate a stored bit value and a selected one of at least two read ports;
- and
- (c) coupling the bit line to a sense amplifier that, when operated simultaneously reads the stored bit values in at least two of the bit cells based on their adjustment of the bit line impedance.
1 more element
A system, comprising:
- (a) a microprocessor having a register file circuit comprising:
- (i) a bit line having an impedance;
- (ii) bit cells coupled to the bit line;
- and
- (iii) a sense amplifier coupled to the bit line, said sense amplifier being sensing at least four different impedance levels on the bit line to read at least two of the bit cells during a single read operation;
- and
- (b) a wireless interface component communicatively linked to the microprocessor.
4 more elements
Dependencies are inferred from the claim text.