Charge pump with ensured pumping capability

A charge pump comprising:

• a plurality of n+1 charge-transfer cells respectively sequentially designated as the first through (n+1)th cells wherein is at least 3, the cells comprising like-polarity field-effect transistors (“FETs”) each having a gate electrode and first and second source/drain (“S/D”) regions separated by a channel portion of a body region where each cell comprises (a) a charge-transfer FET, (b) a first side FET whose first and second S/D regions are respectively coupled to the first S/D and body regions of the charge-transfer FET, and (c) a second side FET whose first and second S/D regions are respectively coupled to the second S/D and body regions of the charge-transfer FET, the cells being arranged in series with the second S/D region of the charge-transfer FET of each cell except the (n+1)th cell coupled to the first S/D region of the charge-transfer FET of the next cell;
• sources of first and second clock signals approximately inverse to each other, the gate electrodes of the first and second side FETs (a) of the first cell being respectively coupled to the second S/D region of the first cell's charge-transfer FET and a selected location in the charge pump, (b) of the (n+1)th cell being respectively coupled to the gate electrode of the (n−1)th cell's charge-transfer FET and the first S/D region of the (n+1)th cell's charge-transfer FET, and (c) of each remaining cell being respectively coupled to the second and first S/D regions of that remaining cell's charge-transfer FET;
• and
• a plurality of n primary capacitive elements respectively corresponding to the first through nth cells, each primary capacitive element coupled between the second S/D region of the charge-transfer FET of the corresponding cell and (i) the source of the first clock signal if that cell is an odd-numbered cell or (ii) the source of the second clock signal if that cell is an even-numbered cell.

A charge pump comprising:

• a plurality of n+1 charge-transfer cells respectively sequentially designated as the first through (n+1)th cells wherein is at least 3, the cells comprising like-polarity field-effect transistors (“FETs”) each having a gate electrode and first and second source/drain (“S/D”) regions separated by a channel portion of a body region where each cell comprises (a) a charge-transfer FET, (b) a first side FET whose first and second S/D regions are respectively coupled to the first S/D and body regions of the charge-transfer FET, and (c) a second side FET whose first and second S/D regions are respectively coupled to the second S/D and body regions of the charge-transfer FET, the cells being arranged in series with the second S/D region of the charge-transfer FET of each cell except the (n+1)th cell coupled to the first S/D region of the charge-transfer FET of the next cell, the gate electrode and second S/D region of the (n+1)th cell's charge-transfer FET being substantially electrically decoupled from each other;
• sources of first and second clock signals approximately inverse to each other, the gate electrodes of the first and second side FETs (a) of the first cell being respectively coupled to the second S/D region of the first cell's charge-transfer FET and a selected location in the charge pump, (b) of the (n+1)th cell being respectively coupled to the gate electrode of the (n+1)th cell's charge-transfer FET and the first S/D region of the (n+1)th cell's charge-transfer FET, and (c) of each remaining cell being respectively coupled to the second and first S/D regions of that remaining cell's charge-transfer FET;
• and
• a plurality of n primary capacitive elements respectively corresponding to the first through nth cells, each primary capacitive element coupled between the second S/D region of the charge-transfer FET of the corresponding cell and (i) the source of the first clock signal if that cell is an odd-numbered cell or (ii) the source of the second clock signal if that cell is an even-numbered cell.

A charge pump comprising:

• a plurality of n+1 charge-transfer cells respectively sequentially designated as the first through (n+1)th cells wherein is at least 3, the cells comprising like-polarity field-effect transistors (“FETs”) each having a gate electrode and first and second source/drain (“S/D”) regions separated by a channel portion of a body region where each cell comprises (a) a charge-transfer FET, (b) a first side FET whose first and second S/D regions are respectively coupled to the first S/D and body regions of the charge-transfer FET, and (c) a second side FET whose first and second S/D regions are respectively coupled to the second S/D and body regions of the charge-transfer FET, the cells being arranged in series with the second S/D region of the charge-transfer FET of each cell except the (n+1)th cell coupled to the first S/D region of the charge-transfer FET of the next cell, the gate electrode and second S/D region of the (n+1)th cell's charge-transfer FET being substantially electrically decoupled from each other;
• sources of first and second clock signals approximately inverse to each other;
• sources of third and fourth clock signals different from the first and second clock signals, the four clock signals all varying substantially between first and second voltage values, the third clock signal being substantially at the first voltage value during pumping operation only during part of each time interval that the first clock signal is substantially at the first voltage value, the fourth clock signal being substantially at the first voltage value during pumping operation only during part of each time interval that the second clock signal is substantially at the first voltage value;
• a plurality of n primary capacitive elements respectively corresponding to the first through nth cells, each primary capacitive element coupled between the second S/D region of the charge-transfer FET of the corresponding cell and (i) the source of the first clock signal if that cell is an odd-numbered cell or (ii) the source of the second clock signal if that cell is an even-numbered cell;
• a plurality of n+1 further capacitive elements respectively corresponding to the n+1 cells, each further capacitive element coupled between the gate electrode of the charge-transfer FET of the corresponding cell and (i) the source of the third clock signal if that cell is an odd-numbered cell or (ii) the source of the fourth clock signal if that cell is an even-numbered cell;
• and
• an additional capacitive element coupled to (i) the source of the first clock signal if n is an even number or (ii) the source of the second clock signal if n is an odd number, the gate electrodes of the first and second side FETs (a) of the first cell being respectively coupled to the second S/D region of the first cell's charge-transfer FET and a selected location in the charge pump, (b) of the (n+1)th cell being respectively coupled to the additional capacitive element and the first S/D region of the (n+1)th cell's charge-transfer FET, and (c) of each remaining cell being respectively coupled to the second and first S/D regions of that remaining cell's charge-transfer FET.

A charge pump comprising:

• a plurality of n+1 charge-transfer cells respectively sequentially designated as the first through (n+1)th cells wherein is at least 3, the cells employing like-polarity field-effect transistors (“FETs”) each having a gate electrode and first and second source/drain (“S/D”) regions separated by a channel portion of a body region where each cell comprises a charge-transfer FET and where each of the first and (n+1)th cells further includes (a) a first side FET whose first and second S/D regions are respectively coupled to the first S/D and body region of that cell's charge-transfer FET and (b) a second side FET whose first and second S/D regions are respectively coupled to the second S/D and body region of that cell's charge-transfer FET, the cells being arranged in series with the second S/D region of the charge-transfer FET of each cell except the (n+1)th cell coupled to the first S/D region of the charge-transfer FET of the next cell;
• sources of first and second clock signals approximately inverse to each other, the gate electrodes of the first side and second FETs (a) of the first cell being respectively coupled to the second S/D region of the first cell's charge-transfer FET and the source of the second clock signal and (b) of the (n+1)th cell being respectively coupled to a selected location in the charge pump and the first S/D region of the (n+1)th cell's charge-transfer;
• and
• a plurality of n primary capacitive elements respectively corresponding to the first through nth cells, each primary capacitive element coupled between the second S/D region of the charge-transfer FET of the corresponding cell and (i) the source of the first clock signal if that cell is an odd-numbered cell or (ii) the source of the second clock signal if that cell is an even-numbered cell.

A charge pump comprising:

• a plurality of n+1 charge-transfer cells respectively sequentially designated as the first through (n+1)th cells wherein is at least 3, the cells employing like-polarity field-effect transistors (“FETs”) each having a gate electrode and first and second source/drain (“S/D”) regions separated by a channel portion of a body region where each cell comprises a charge-transfer FET and where each of the first and (n+1)th cells further includes (a) a first side FET whose first and second S/D regions are respectively coupled to the first S/D and body region of that cell's charge-transfer FET and (b) a second side FET whose first and second S/D regions are respectively coupled to the second S/D and body region of that cell's charge-transfer FET, the cells being arranged in series with the second S/D region of the charge-transfer FET of each cell except the (n+1)th cell coupled to the first S/D region of the charge-transfer FET of the next cell;
• sources of first and second clock signals approximately inverse to each other, the gate electrodes of the first and second side FETs (a) of the first cell being respectively coupled to the second S/D region of the first cell's charge-transfer FET and a selected location in the charge pump and (b) of the (n+1)th cell being respectively coupled to the second S/D region of the (n−1)th cell's charge-transfer FET and the first S/D region of the (n+1)th cell's charge-transfer FET;
• and
• a plurality of n primary capacitive elements respectively corresponding to the first through nth cells, each primary capacitive element coupled between the second S/D region of the charge-transfer FET of the corresponding cell and (i) the source of the first clock signal if that cell is an odd-numbered cell or (ii) the source of the second clock signal if that cell is an even-numbered cell.