Readout circuit and nonvolatile semiconductor memory device
AssigneeNEC Electronics Corporation
InventorYasuhiro Tonda
Life of this patent
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Abstract
A readout circuit has: a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through the memory cell transistor and a reference current flowing through a dummy cell transistor; and a voltage control circuit configured to apply a first voltage to a gate of the dummy cell transistor in a read operation. The memory cell transistor has a control gate and a floating gate. The voltage control circuit sets the first voltage such that a voltage between the gate and a source of the dummy cell transistor is lower than a voltage between the control gate and a source of the memory cell transistor.
Claims20
A readout circuit comprising:
- a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through said memory cell transistor and a reference current flowing through a dummy cell transistor;
- and
- a voltage control circuit configured to apply a first voltage to a gate of said dummy cell transistor in a read operation,
- wherein said memory cell transistor has a control gate and a floating gate, and
- said voltage control circuit sets said first voltage such that a voltage between said gate and a source of said dummy cell transistor is lower than a second voltage between said control gate and a source of said memory cell transistor.
A nonvolatile semiconductor memory device comprising:
- a memory cell transistor having a control gate and a floating gate;
- a dummy cell transistor;
- a sense amplifier circuit configured to sense a data stored in said memory cell transistor based on a current flowing through said memory cell transistor and a reference current flowing through said dummy cell transistor;
- and
- a voltage control circuit configured to apply a first voltage to a gate of said dummy cell transistor in a read operation,
- wherein said voltage control circuit sets said first voltage such that a voltage between said gate and a source of said dummy cell transistor is lower than a second voltage between said control gate and a source of said memory cell transistor.
A readout circuit which senses a data stored in a memory cell based on a current flowing through a memory cell transistor having a control gate and a floating gate and a current flowing through a dummy cell transistor, characterized in that a voltage between a gate and a source of said dummy cell transistor is lower than a voltage between said control gate and a source of said memory cell transistor.
Dependencies are inferred from the claim text.