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US 2006/0133170 A1Published application
Memory circuit
AssigneePanasonic Corporation
InventorYuuichirou Ikeda
Life of this patent
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Abstract
The memory circuit comprises: a single or a plurality of reading-out port(s); a single or a plurality of writing port(s); a crosstalk-glitch suppressor circuit for suppressing crosstalk glitch between internal signal lines of each of the ports; and a control device for controlling capacity of the crosstalk-glitch suppressor circuit.
Claims19
A memory circuit, comprising:
- a single or a plurality of reading-out port(s);
- a single or a plurality of writing port(s);
- a crosstalk-glitch suppressor circuit for suppressing crosstalk glitch between internal signal lines of each of said ports;
- and a control device for controlling capacity of said crosstalk-glitch suppressor circuit.
1 more element
Dependencies are inferred from the claim text.