Semiconductor memory with wordline timing
AssigneeMicron Technology, Inc.
InventorRamandeep Sawhney
Life of this patent
Estimating the term…
Abstract
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.
Claims29
A method of controlling a wordline decoder in a memory device, comprising:
- activating the wordline decoder based on the state of an isolation signal local to a memory array to be accessed;
- and
- deactivating the wordline decoder based on the state of a row access signal.
A method of reducing data corruption in a memory device, comprising:
- providing a timing circuit in the memory device;
- connecting a wordline decoder to a memory array;
- linking activation of the wordline decoder to the timing circuit;
- and
- producing a wordline activation signal from the timing circuit based on a nearby ISO signal.
A timing, integrated circuit, comprising:
- an input adapted to receive a row access signal and a sense amplifier isolation signal;
- and
- an output adapted to connect an address decoder, wherein the timing circuit activates the address decoder based on a state of the row access signal and the sense amplifier isolation signal.
An integrated circuit adapted to time activation of a wordline decoder to a sense amplifier isolation signal, comprising:
- a first input connected to a sense amplifier isolation signal line;
- a second input adapted to receive a memory access control signal;
- an output adapted to activate/deactivate a wordline decoder based on the first input and the second input.
A timing circuit, comprising:
- a delay circuit connected to a sense amplifier isolation signal line;
- a first input connected to the delay circuit;
- a second input adapted to receive at least one input signal;
- and
- an output based on the first input and the second input and connected to an address decoder, wherein the timing circuit activates the address decoder based on the first input signal and the second input signal.
An integrated circuit adapted to time activation of a wordline decoder to a sense amplifier isolation signal, comprising:
- a first input adapted to receive a sense amplifier isolation signal;
- a second input adapted to receive a memory access control signal;
- a timing output adapted to activate/deactivate a wordline decoder based on the first input and the second input.
A method comprising:
- activating a wordline in a memory device based on the state of an isolation signal local to a memory array to be accessed;
- and
- deactivating the wordline based on the state of a row access signal (RAS).
Dependencies are inferred from the claim text.