Self-latched control circuit for memory program operation

A memory programming control circuit connected to a memory cell via a data line for controlling a programming current in a programming operation of the memory cell, the memory programming control circuit comprising:

• a programming enable device connected to a positive power supply for selectively applying a pull-up current on the data line;
• a self-latch module connected between the programming enable device and the memory cell for preventing the pull-up current from flowing to the memory cell through the data line, when the memory cell is programmed with a predetermined data bit;
• and
• a data-in buffer coupled to the data line for selectively discharging the data line when the predetermined data bit is a logic low.

A memory programming control circuit connected to a plurality of memory cells via a plurality of data lines for controlling at least one programming current in a program operation of the memory cells, the memory programming control circuit comprising:

• at least one bit line selection multiplexer for selecting a predetermined data line to charge a predetermined memory cell;
• a pull-up PMOS transistor connected to a positive power supply for selectively applying a pull-up current through its source and drain to the data line when a gate thereof is activated by a program reference control signal;
• a self-latch module connected between the pull-up PMOS transistor and the memory cell for preventing the pull-up current from flowing to the memory cell through the data line, when the memory cell is programmed with a predetermined data bit;
• and
• a data-in buffer coupled to the data line through the bit line selection multiplexer for selectively discharging the data line when the predetermined data bit is a logic low,
• wherein the self-latch module prevents the pull-up current from flowing into the predetermined data line when the data-in buffer discharges the data line.