Bufferless writing of data to memory
AssigneeHewlett-Packard Development Company, L.P.
InventorsFraser Dickin, Weng Loh
Life of this patent
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Abstract
This invention provides a processor 900 for writing data contained in payload data 1006 of a data packet 1000 to memory, especially for use as the central processing unit of a memory tag 1200. The processor 900 does not include a write buffer. The processor 900 comprises a first register 910 adapted to latch first data corresponding to a segment of the payload data; and a second register 224 adapted to receive second data from the payload data 1006 to enable the validity of the data latched into the first register 910 to be established before data is written to memory. A memory device, a method for writing data contained in payload data 1006, a data packet 1000, a method of writing data into a non-volatile memory and a memory tag are also provided.
Claims69
A processor for writing data contained in payload data of a data packet to memory, comprising:
- a first register adapted to latch first data corresponding to a segment of the payload data;
- and
- a second register adapted to receive second data from the payload data to enable the validity of the data latched into the first register to be established before data is written to memory.
A method of processing, in a processor, a data packet, comprising:
- (a) receiving first data in the processor corresponding to a segment of payload data in the data packet;
- (b) receiving second data in the processor from the payload data;
- (c) processing the second data to enable the validity of the first data to be established;
- and
- (d) if the first data is valid, outputting the first data to enable the first data to be written to memory.
A packet for the transmission of data to a processor, comprising a data payload including a plurality of data segments, each data segment followed by a check field corresponding to its preceding data segment.
A method of writing data into a non-volatile memory, comprising the steps of:
- receiving a first segment of the data into a data register;
- receiving a second segment of the data into the data register after an interval of time after receiving the first segment;
- and
- writing the first segment into the memory and clearing the data register to receive the second segment in the interval of time between receiving the first segment and receiving the second segment.
A memory tag for receiving data, comprising:
- a data register configured to receive a first segment of the data and a second segment of the data after an interval of time after receiving the first segment of the data;
- and
- an array of non-volatile memory for receiving the first segment of the data from the data register in the interval of time,
- wherein the data register is cleared in the interval of time after the non-volatile memory has received the first segment of the data.
A method of writing data into non-volatile memory, comprising:
- obtaining configuration data on the non-volatile memory;
- and
- formatting the data to be written into the non-volatile memory by inserting padding data between segments of the data,
- wherein the length of padding data inserted between each data segment is varied in accordance with the configuration data.
Apparatus for writing data to a non-volatile memory comprising:
- a transceiver adapted to transmit data to a memory tag in which the non-volatile memory resides and receive configuration data on the non-volatile memory;
- and
- a processor connected to the transceiver configured to format the data to be written into the non-volatile memory in accordance with the configuration data.
Dependencies are inferred from the claim text.