Memory device
AssigneeMacronix International Co., Ltd.
InventorsYen-Hao Shih, Hang-Ting Lue
Life of this patent
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Abstract
A method of stabilizing a memory device comprises trapping a plurality of electric charges in a charge trapping layer of the memory device. The charge trapping layer is positioned between a transistor control gate and a transistor channel region. The method further comprises applying a negative voltage bias to the transistor control gate. In another embodiment, the method further comprises performing a baking process on the memory device. The method further comprises performing a memory operation on the memory device.
Claims40
A method of enhancing memory retention in a memory device, comprising:
- trapping a plurality of electric charges in a charge trapping layer of the memory device, the charge trapping layer positioned between a transistor control gate and a transistor channel region;
- applying a negative voltage bias to the transistor control gate to cause electric charges to move from a relatively shallow trap to a substrate;
- and
- performing a memory operation on the memory device.
A method of stabilizing a memory device, comprising:
- trapping a plurality of electric charges in a charge trapping layer of the memory device, the charge trapping layer positioned between a transistor control gate and a transistor channel region;
- subjecting the memory device to a high-temperature baking process to cause electric charges to move from a relatively shallow trap site to a relatively deep trap site;
- and
- performing a memory operation on the memory device.
A method comprising:
- trapping a plurality of electric charges in a charge trapping layer of a transistor, wherein the charge trapping layer is separated from a transistor control gate and a transistor channel region by a gate insulator;
- and
- performing a charge stabilization operation on the electric charges trapped in the charge trapping layer to reduce the quantity of electric charges in shallow trap sites.
An apparatus comprising:
- a transistor device having a control gate and a channel region;
- a gate insulator separating the control gate from the channel region;
- and
- a plurality of electric charges trapped in a charge trapping layer of the gate insulator, wherein the plurality of charges have an average trapping energy such that a transistor threshold voltage Vth of the transistor device decreases by between approximately 0.01 volts and approximately 0.40 volts within a 1000-second period.
Dependencies are inferred from the claim text.