Method for programming and erasing an NROM cell
AssigneeMicron Technology, Inc.
InventorAndrei Mihnea
Life of this patent
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Abstract
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.
Claims18
A method for operating a CMOS system comprising a processor coupled to a CMOS memory device comprising a plurality of nitride read only memory (NROM) cells, each NROM cell having a gate and two source/drain regions, the method comprising:
- applying a ramp voltage to the gate of each NROM cell to be programmed;
- applying a constant voltage to one of the two source/drain regions of each NROM cell to be programmed;
- and
- applying a ground potential to the remaining source/drain region of each NROM cell to be programmed.
A memory system comprising:
- a CMOS processor for generating control, data, and address signals;
- and
- a CMOS memory device coupled to the processor and having a plurality of nitride read only memory (NROM) cells, each NROM cell comprising:
- a gate coupled to a ramp voltage;
- a first source/drain region coupled to a constant voltage;
- and
- a second source/drain region coupled to a ground potential.
A method for operating a CMOS system comprising a processor coupled to a CMOS memory device comprising a plurality of nitride read only memory (NROM) cells, each NROM cell having a gate and two source/drain regions, the method comprising:
- applying a constant voltage to the gate of each NROM cell to be erased;
- applying a constant positive current into a first of the source/drain regions of each NROM cell to be erased;
- and
- floating the remaining source/drain region of each NROM cell to be erased.
A method for operating a CMOS memory system comprising a processor coupled to an NROM array that comprises a plurality of NROM cells, each NROM cell having a gate and two source/drain regions, the method comprising:
- applying a constant voltage to the gate of each NROM cell to be erased;
- applying a constant positive current into a first of the source/drain regions of each NROM cell to be erased;
- and
- applying a ground potential to the remaining source/drain region of each NROM cell to be erased.
A method for operating a memory system comprising a CMOS nitride read only memory (NROM) memory device coupled to a processor, the memory device having a CMOS memory array comprising a plurality of NROM cells, each NROM cell having a gate and two source/drain regions, the method comprising:
- applying a constant voltage to the gate of each NROM cell to be erased;
- applying a constant positive current into a first source/drain region of each NROM cell to be erased;
- and
- coupling the remaining source/drain region to the first source/drain region or each NROM cell to be erased.
A method for operating a memory system comprising a CMOS nitride read only memory (NROM) memory device coupled to a processor, the memory device having a CMOS memory array comprising a plurality of NROM cells, each NROM cell having a gate and two source/drain regions, the method comprising:
- applying a constant voltage to a first of the source/drain regions of each NROM cell to be erased;
- applying a negatively ramped voltage to the gate of each NROM cell to be erased;
- and
- coupling the remaining source/drain region to the first source/drain region of each NROM cell to be erased.
A method for operating a memory system comprising a CMOS nitride read only memory (NROM) memory device coupled to a processor, the memory device having a CMOS memory array comprising a plurality of NROM cells, each NROM cell having a gate and two source/drain regions, the method comprising:
- applying a constant voltage to a first of the source/drain regions of each NROM cell to be erased;
- applying a negatively ramped voltage to the gate of each NROM cell to be erased;
- and
- applying a ground potential to the remaining source/drain region of each NROM cell to be erased.
Dependencies are inferred from the claim text.