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US 2006/0133150 A1Published application
Semiconductor memory device capable of setting a negative threshold voltage
AssigneeKabushiki Kaisha Toshiba
InventorNoboru Shibata
Life of this patent
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Abstract
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.
Claims22
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in a matrix, the memory cells being connected to word lines and bit lines;
- and
- a control circuit which controls the potentials of the word lines and bit lines and which, when performing a read operation on the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in a matrix, the memory cells being connected to word lines and bit lines;
- a control circuit which controls the potentials of the word lines, the bit lines, a source line, and a well;
- and
- a constant voltage generating circuit which generates a first voltage and a second voltage,
- wherein each of the memory cells has an n number of states, including a first state, a second state, an n-th state (n is a natural number equal to 2 or more) and the control circuit, when reading the first state, the second state, . . . , a k-th state (k≦n where k is a natural number), supplies the first voltage generated by the constant voltage generating circuit to the source line of the memory cell array and, when reading a (k+1)-th state to the n-th state, supplies the second voltage to the source line of the memory cell.
2 more elements
Dependencies are inferred from the claim text.