Single-event upset tolerant static random access memory cell

A memory device comprising:

• a sense amplifier;
• and
• a plurality of memory cells coupled to said sense amplifier, wherein one of said memory cells include:
• a first set of access transistors coupled to a first bitline;
• a second set of access transistors coupled to a second bitline, wherein said second bitline is complementary to said first bitline;
• a first set of dual-path inverters coupled to said first set of access transistors, wherein said first set of dual-path inverters includes a first transistor connected to a second transistor in series and a third transistor connected to a fourth transistor in series;
• and
• a second set of dual-path inverters coupled to said second set of access transistors, wherein said second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series and a seventh transistor connected to an eighth transistor in series.

An electronic system comprising:

• a plurality of logic circuits;
• and
• a memory device coupled to said logic circuits, wherein said memory device includes a plurality of memory cells and a sense amplifier, wherein said one of said memory cells include:
• a first set of access transistors coupled to a first bitline;
• a second set of access transistors coupled to a second bitline, wherein said second bitline is complementary to said first bitline;
• a first set of dual-path inverters coupled to said first set of access transistors, wherein said first set of dual-path inverters includes a first transistor connected to a second transistor in series and a third transistor connected to a fourth transistor in series;
• and
• a second set of dual-path inverters coupled to said second set of access transistors, wherein said second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series and a seventh transistor connected to an eighth transistor in series.