Low voltage semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorsHee-Bok Kang, Jin-Hong Ahn
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference metal oxide semiconductor (MOS) transistor for connecting the reference capacitor to the bit line, and a second reference MOS transistor for connecting the reference capacitor to the bit line bar; and a third reference MOS transistor coupled to the reference cell block for charging the reference capacitor with a reference voltage.
Claims32
A semiconductor memory device having a cell array area for reading or storing data, comprising:
- a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data;
- a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference metal oxide semiconductor (MOS) transistor for connecting the reference capacitor to the bit line, and a second reference MOS transistor for connecting the reference capacitor to the bit line bar;
- and
- a third reference MOS transistor coupled to the reference cell block for charging the reference capacitor with a reference voltage.
A semiconductor memory device having a plurality of bit line pairs with a folded bit line architecture, the semiconductor memory device comprising:
- a plurality of normal cells including a normal capacitor and a normal MOS transistor for connecting the normal capacitor to one of a bit line and a bit line bar;
- a plurality of reference cells including a reference capacitor, a first reference MOS transistor for connecting a corresponding bit line to a first node of the reference capacitor, and a second reference MOS transistor for connecting the first node of the reference capacitor to the bit line bar adjacent to the bit line;
- a reference voltage supply unit for supplying a reference voltage to a second node of the reference capacitor provided at each of the reference cells;
- at least two precharge MOS transistors for supplying the reference voltage to the first node of the reference capacitor provided at each of the reference cell during a precharge period;
- and
- a metal shunt line for maintaining a drain of each of the precharge MOS transistor at the same voltage level.
Dependencies are inferred from the claim text.