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US 2006/0133130 A1Published application
Memory circuit receivers activated by enable circuit
AssigneeInfineon Technologies AG
InventorAlessandro Minzoni
Life of this patent
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Abstract
A memory circuit comprises an enable circuit and a receiver. The enable circuit is configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level. The receiver is configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal.
Claims21
A memory circuit comprising:
- an enable circuit configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level;
- and
- a receiver configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal.
A memory circuit comprising:
- means for receiving an internal clock signal and providing an enable signal having a first logic level and a second logic level;
- and
- means for activating a receiver in response to the first logic level of the enable signal and deactivating the receiver in response to the second logic level of the enable signal.
A memory circuit comprising:
- an address receiver configured to be selectively activated in response to an enable signal;
- a command receiver configured to be selectively activated in response to the enable signal;
- a bank select receiver configured to be selectively activated in response to the enable signal;
- a clock receiver configured to receive a differential external clock signal and provide an internal clock signal;
- an enable circuit configured to receive the internal clock signal and provide the enable signal to activate the address receiver, the command receiver, and the bank select receiver during a setup and hold time of the address receiver, the command receiver, and the bank select receiver;
- and
- a memory coupled the address receiver, the command receiver, and the bank select receiver.
4 more elements
A method for receiving a signal in a memory circuit, the method comprising:
- receiving an internal clock signal and providing an enable signal having a first logic level and a second logic level;
- and
- activating a receiver in response to the first logic level of the enable signal and deactivating the receiver in response to the second logic level of the enable signal.
A memory circuit for low power applications comprising:
- an address receiver configured to be selectively activated to collect and decode address signals and deactivated to conserve power between the address signals in response to an enable signal;
- a command receiver configured to be selectively activated to collect and decode command signals and deactivated to conserve power between command signals in response to the enable signal;
- a bank select receiver configured to be selectively activated to collect and decode bank select signals and deactivated to conserve power between bank select signals in response to the enable signal;
- a clock receiver configured to receive a differential external clock signal and provide an internal clock signal;
- an enable circuit configured to receive the internal clock signal and provide the enable signal to activate the address receiver, the command receiver, and the bank select receiver during a setup and hold time of the address receiver, the command receiver, and the bank select receiver;
- and
- a memory coupled the address receiver, the command receiver, and the bank select receiver.
4 more elements
Dependencies are inferred from the claim text.