Apparatus and method for memory operations using address-dependent conditions
AssigneeMatrix Semiconductor, Inc.
InventorsKenneth So, Luca Fasoli, Roy Scheuerlein
Life of this patent
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Abstract
An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.
Claims45
An apparatus comprising:
- a plurality of word lines and word line drivers;
- a plurality of bit lines and bit line drivers;
- a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line;
- and
- circuitry operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver.
An apparatus comprising:
- a plurality of word lines and word line drivers;
- a plurality of bit lines and bit line drivers;
- a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line;
- and
- circuitry operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver.
An apparatus comprising:
- a plurality of word lines and word line drivers;
- a plurality of bit lines and bit line drivers;
- a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line;
- and
- circuitry operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to one or both of a word line driver and a bit line driver.
Dependencies are inferred from the claim text.