Semiconductor memory device and method of making design change to semiconductor chip
AssigneeElpida Memory, Inc.
InventorYoshinori Haraguchi
Life of this patent
Estimating the term…
Abstract
The positions of the main driver 10, the output pad 20 and the first buffer 61 and the second buffer 62 are changed from the central region 111 to the peripheral region 120, and the first control signal line 31 and the second control signal line 32 are elongated. The distance between the output pad 20 and the main driver 10 is maintained so that the resistance between the output pad 20 and the main driver 10 does not increase.
Claims11
A semiconductor chip, comprising:
- a main driver comprising a pMOSFET, an nMOSFET and an output node, wherein the pMOSFET has a first gate for receiving a first control signal and the nMOSFET has a second gate for receiving a second control signal;
- an output pad coupled to the output node;
- a first control signal line for transmitting the first control signal;
- a second control signal line for transmitting the second control signal;
- a first predriver for driving the first control signal line;
- a second predriver for driving the second control signal line;
- the first control signal line is arranged physically next to and physically in parallel with the second control signal line.
A method of making design change to a semiconductor chip comprising a main driver, an output pad, a first control signal line, a second control signal line, a first predriver and a second predriver;
- wherein a main driver comprises an output node, a pMOSFET and an nMOSFET comprises a first gate for receiving a first control signal, the nMOSFET comprises a second gate for receiving a second control signal, the output pad is coupled to the output node, the first control signal line transmits the first control signal, the second control signal line transmits the second control signal, the first predriver drives the first control signal line, the second predriver drives the second control signal line, comprising:
- preparing layouts of the semiconductor chip;
- and
- arranging the first control signal line physically next to and physically in parallel with the second control signal line.
Dependencies are inferred from the claim text.