Method and apparatus to read information from a content addressable memory (CAM) cell
AssigneeIntel Corporation
InventorsChristopher Haid, Tahmid Rahman, Edward Babb
Life of this patent
Estimating the term…
Abstract
A method and apparatus to read information from a content addressable memory (CAM) cell of a nonvolatile memory is provided. The apparatus may be a nonvolatile memory that may include a first content addressable memory (CAM) cell, wherein the first CAM cell comprises a latch to store volatile binary information and to provide the volatile binary information to an output terminal of the first CAM cell. Other embodiments are described and claimed.
Claims20
(canceled)
The nonvolatile memory of claim 4, wherein the nonvolatile memory is a flash electrically erasable programmable read-only memory (EEPROM).
The nonvolatile memory of claim 4, wherein the latch is a bistable multivibrator circuit.
A nonvolatile memory, comprising
- a first content addressable memory (CAM) cell, wherein the first CAM cell comprises a latch to store volatile binary information and to provide the volatile binary information to an output terminal of the first CAM cell, wherein the first CAM cell further comprises:
- a first nonvolatile memory cell having a floating gate, a control gate, a drain, and a source coupled to ground;
- a second nonvolatile memory cell having a floating gate, a control gate coupled to the control gate of the first nonvolatile memory cell, a drain, and a source coupled to ground;
- a first transistor having a gate, a source coupled to the drain of the first nonvolatile memory cell, and a source;
- and
- a second transistor having a gate coupled to the gate of the first transistor, a source coupled to the drain of the second nonvolatile memory cell, and a source;
- a third transistor having a gate, a drain coupled to a drain of the first transistor, and a source coupled to receive a voltage potential;
- and
- a fourth transistor having a gate coupled to the drain of the third transistor, a drain coupled to coupled to the gate of the third transistor, and a source coupled to receive the voltage potential, wherein the drain of the fourth transistor is coupled to the output terminal of the first CAM cell.
A method, comprising:
- reading information from a first CAM cell of a plurality of CAM cells of a nonvolatile memory while simultaneously programming a second CAM cell of the plurality of CAM cells, wherein the first CAM cell comprises a latch to store volatile binary information and to provide the volatile binary information to an output terminal of the CAM cell.
(canceled)
The system of claim 20, wherein the system is a wireless phone.
The nonvolatile memory of claim 20, wherein the latch is a bistable multivibrator circuit.
A system comprising:
- a processor;
- an antenna coupled to the processor, and
- a nonvolatile flash electrically erasable programmable read-only memory (EEPROM) coupled to the processor, comprising a first content addressable memory (CAM) cell, wherein the first CAM cell comprises a latch to store volatile binary information and to provide the volatile binary information to an output terminal of the first CAM cell,
- wherein the first CAM cell further comprises
- a first nonvolatile memory cell having a floating gate, a control gate, a drain, and a source coupled to ground;
- a second nonvolatile memory cell having a floating gate, a control gate coupled to the control gate of the first nonvolatile memory cell, a drain, and a source coupled to ground;
- a first transistor having a gate, a source coupled to the drain of the first nonvolatile memory cell, and a source;
- a second transistor having a gate coupled to the gate of the first transistor, a source coupled to the drain of the second nonvolatile memory cell, and a source;
- a third transistor having a gate, a drain coupled to a drain of the first transistor, and a source coupled to receive a voltage potential;
- and
- a fourth transistor having a gate coupled to the drain of the third transistor, a drain coupled to coupled to the gate of the third transistor, and a source coupled to receive the voltage potential, wherein the drain of the fourth transistor is coupled to the output terminal of the first CAM cell.
Dependencies are inferred from the claim text.