Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal
AssigneeNokia Corporation
InventorsMatti Floman, Jani Klint
Life of this patent
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Abstract
An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n≧2.
Claims43
A circuit, comprising a plurality of terminals for coupling to signal lines, where one of the signal lines is an input signal line that conveys a clock signal, and where at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n≧2.
A method to input information to a circuit via a plurality of terminals coupled to signal lines, comprising:
- applying a clock signal to one signal line;
- and
- encoding information on at least one other signal line by setting a level of the at least one other signal line so as to be in a predetermined state at each of n consecutive edge transitions of the clock signal, where n≧2.
A method to receive information at an integrated circuit, comprising:
- receiving a clock signal;
- sampling the state of a signal appearing on at least one integrated circuit terminal at each of n consecutive edge transitions of the clock signal, where n≧2;
- and
- correlating the sampled states with information encoded by the at least one signal.
A device comprising at least one circuit package that comprises a plurality of terminals for coupling to signal lines, where one of the signal lines is an input signal line that conveys a clock signal, and where at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n≧2.
A method to operate a memory unit, comprising:
- applying a clock signal to one memory unit input signal line;
- and
- encoding information on at least one other memory unit input signal line by setting a level of the at least one other memory unit input signal line so as to be in a predetermined state at each of n consecutive edge transitions of the clock signal, where n≧2, where the predetermined state is one selected to wake up the memory unit from a power down mode.
A memory unit, comprising:
- a memory unit input signal line for coupling to a clock signal;
- and
- at least one other memory unit input signal line for receiving encoded information by inputting a level on the at least one other memory unit input signal line so as to be in a predetermined state at each of n consecutive edge transitions of the clock signal, where n≧2, and where the predetermined state is one selected to wake up the memory unit from a power down mode.
Dependencies are inferred from the claim text.