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US 2006/0132246 A1Published application
Glitch free controlled ring oscillator and associated methods
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsNaveen Tiwari, Balwant Singh
Life of this patent
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Abstract
A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.
Claims8
1-7. (canceled)
A ring oscillator comprising:
- a gating and inverter stage;
- a programmable delay chain;
- and
- a latch stage coupled between said programmable delay chain and said gating and inverter stage for registering a clock state at a time of disabling the ring oscillator and setting an output of the ring oscillator to the clock state.
1 more element
A ring oscillator comprising:
- a gating and inverting stage;
- a programmable delay chain;
- a latch stage between said programmable delay chain and said gating and inverting stage;
- a control block for generating a control signal and comprising a logic gate and a matching delay for registering a clock state at a time of disabling the ring oscillator and setting an output of the ring oscillator to the clock state;
- said latch and gating and inverting stage being responsive to the control signal for enabling/disabling the ring oscillator;
- and
- a pulling down circuit comprising a second programmable delay chain and logic gates for generating the clock state, the logic gates coupled to said gating and inverting stage for pulling down the clock state if the clock state is high after a period sufficient to avoid at least one of a false edge and a glitch.
4 more elements
A method for providing a reduced glitch signal output from a ring oscillator, the method comprising:
- propagating a signal to generate a clock through a programmable delay chain of the ring oscillator;
- and
- registering a clock state at a time of disabling the ring oscillator and setting an output of the ring oscillator to the clock state to provide the reduced glitch signal output.
Dependencies are inferred from the claim text.