Charge pump circuit
AssigneeMacronix International Co., Ltd.
InventorsKuan-Yeu Chen, Yi-Ti Wang
Life of this patent
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Abstract
In an embodiment, a charge pump circuit comprises a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor. The higher efficiency the re-charge MOSFET is, the lower the gate level of pass transistor is. Thus, the charge sharing efficiency becomes better, and the body effect will be eliminated. The following pump stage is the same as the first pump stage. In addition, this embodiment is implemented by PMOSFET only; therefore, only single well is needed and then a small layout area can be achieved. Consequently, a high efficiency negative pump can be obtained.
Claims16
A charge pump circuit, comprising:
- a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor;
- and
- a second pump stage coupled to the first pump stage, the second pump stage including a second sub-pump coupled to a second pre-charge MOSFET transistor, wherein the second sub-pump is used to pump down a gate of the second pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the second pre-charge MOSFET transistor.
A charge pump circuit, comprising:
- a pre-charge transistor having a source, a gate, and a drain;
- a discharge transistor coupled to the gate of the pre-charge transistor, wherein the discharge transistor selectively discharges the pre-charge transistor;
- a pass transistor coupled to the source of the pre-charge transistor;
- and
- an initialization transistor coupled to the pass transistor, wherein the initialization transistor initializes the drain of the pass transistor.
A memory device, comprising:
- non-volatile memory cells;
- a charge pump coupled to the memory cells to erase the memory cells, the charge pump comprising;
- a pre-charge transistor having a source, a gate, and a drain;
- a discharge transistor coupled to the gate of the pre-charge transistor, wherein the discharge transistor selectively discharges the pre-charge transistor;
- a pass transistor coupled to the source of the pre-charge transistor;
- and
- an initialization transistor coupled to the pass transistor, wherein the initialization transistor initializes the drain of the pass transistor.
Dependencies are inferred from the claim text.