Semiconductor circuit, operating method for the same, and delay time control system circuit

An operating method for a semiconductor circuit comprising:

• executing detailed routing, a delay extraction, a delay calculation, and a delay analysis for a variable capacitance embedded buffer adjacent the center of a variable width of delay time adjustment;
• determining whether there is a to-be-delayed delay time of the semiconductor circuit;
• calculating a to-be-delayed delay time when there is a to-be-delayed delay time as analysis results;
• calculating a to-be-expedited delay time when there is a to-be-expedited delay time as analysis results;
• and
• replacing a referred cell of the semiconductor circuit based on the resulting delay time,
• wherein
• the semiconductor circuit is connected between an input pad and an output pad and comprises:
• a first buffer connected between the input pad and the output pad;
• and
• a plurality of capacitances connectable in parallel between a fixed potential and a current flow path positioned between the first buffer and the output pad,
• wherein
• a connection between each of the plurality of capacitances and the output pad is respectively controlled.

A delay time control system circuit, comprising:

• a plurality of control terminal-equipped/variable capacitance embedded buffers connected between an input pad and an output pad of a semiconductor circuit and configuring the semiconductor circuit comprising:
• a first buffer connected between the input pad and the output pad,
• a plurality of capacitances connectable in parallel between a fixed potential and a current flow path positioned between the first buffer and the output pad, and
• a plurality of control terminals, each connected in series between a corresponding one of the plurality of capacitances and the output pad, and each individually controlling a connection between a corresponding one of the plurality of capacitances and the output pad so that connection between the corresponding one of the plurality of capacitances and the output pad can be controlled;
• an externally writable memory;
• and
• a plurality of control lines connected between the externally writable memory and each of the plurality of control terminals within the plurality of control terminal-equipped/variable capacitance embedded buffers, wherein
• a connection of each of the plurality of capacitances connected in parallel between the current flow path and the fixed potential is controlled so as to externally adjust delay time of the plurality of control terminal-equipped/variable capacitance embedded buffers.