US 2006/0132209 A1 · CMOS master/slave flip-flop with integrated multiplexor

Abstract

A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.

Claims14

Dependent claims

A master-slave latch comprising:

a data output;
a first data input;
a second data input;
a data select input for selecting one of said first and second data inputs and ignoring the other of said first and second data inputs;
a clock input, wherein said master-slave latch is effective for tracking a signal at the selected one of said first and second data inputs when said clock input is at a first logic state, and for transferring to said data output the tracked result when the clock input transitions from said first logic state to a second logic state;
wherein said master-slave latch is further effective for maintaining the transferred tracked result at said data output unchanged during a transition at said clock input from said second logic state to said first logic state.

3 more elements

A current-mode master-slave latch comprising

a master latch block incorporating a multiplexing function and having:
a data selection block having a first data input, a second data input, a clock input, and a data select input for selecting one of said first and second data inputs and ignoring the other of said first and second data inputs in response to being enabled by said clock input being at a first logic state;
a first data latch for latching in the selected one of said first and second data inputs in response to being enabled by said clock being at a second logic state;
a first current source, wherein said data selection block and said first data latch are enabled and disabled by being coupled to and decoupled from said first current source in accordance with said clock input;
wherein said data selection block is enabled when said first data latch is disabled, and said data selection block is disabled when said first data latch is enabled;
a data transfer block for transferring the latched contents of said first data latch onto an intermediary output when enabled in accordance with said clock input, and for isolating said first data latch from said intermediary output when disabled in accordance with said clock input;
a second current source, wherein said data transfer block is enabled and disabled by being coupled to and decoupled from said second current source in accordance with said dock input;
wherein said data transfer block is enabled when said first data latch is enabled, and is disabled when said first data latch is disabled,
a second data latch for, when enabled, latching in the contents of said intermediary output and outputting the latched contents onto a data output, and for, when disabled, permitting the contents of said intermediary output to be coupled directly to said data output;
wherein said second data latch is enabled and disabled by being coupled to and decoupled from said second current source in accordance with said clock input;
and
wherein said second data latch is enabled when said data selection block is enabled, and is disabled when said data selection block is disabled.

9 more elements

Dependencies are inferred from the claim text.

CMOS master/slave flip-flop with integrated multiplexor

Life of this patent

CMOS master/slave flip-flop with integrated multiplexor

Life of this patent

Abstract

Claims14