Controllable idle time current mirror circuit for switching regulators, phase-locked loops, and delay-locked loops

Abstract

The four types of the controllable idle time current mirror circuits are presented with an improvement in productivity, performance, cost, chip area, power consumption, and design time. The controllable idle time current mirror circuits basically include a sensing block, triggering transistors, current mirror, current source, a n-bit control circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensing gate, the triggering transistors provide a current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. Time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all controllable idle time current mirror circuits provide a controllable reduction in the difference between the initial condition and the expected condition in order to solve many drawbacks simultaneously. In addition, all the controllable idle time current mirror circuits within applied systems control how fast the applied systems come into regulation or lock. Thus, all the controllable idle time current mirror circuits presented achieve a fast controllable lock-in time, a short controllable start-up time, a controllable reduction in power and time, a significant reduction in design simulation time, an improvement in productivity, and a higher performance.

Dependencies are inferred from the claim text.