Differential clock correction
AssigneeIntel Corporation
InventorVijay Khawshe
Life of this patent
Estimating the term…
Abstract
A method, system, and apparatus are disclosed that correct a differential clock signal. A clock correction circuit may determine a DC correction for a first clock signal of a differential clock signal and a DC correction for a second clock signal of a differential clock signal based upon a DC level of the differential clock signal. The clock correction circuit may adjust a DC level of the first clock signal based upon the DC correction for the first clock signal and a DC level of the second clock signal based upon the DC correction for the second clock signal to substantially maintain a duty cycle of the differential clock signal.
Claims20
A method comprising
- determining a DC correction for a first clock signal of a differential clock signal and a DC correction for a second clock signal of a differential clock signal based upon a DC level of the differential clock signal, and
- adjusting a DC level of the first clock signal based upon the DC correction for the first clock signal and a DC level of the second clock signal based upon the DC correction for the second clock signal to substantially maintain a duty cycle of the differential clock signal.
An apparatus comprising:
- a correction generation circuit to generate a first correction signal for a first clock signal of a differential clock signal and to generate a second correction signal for a second clock signal of the differential clock signal, and
- a level shifter to adjust a duty cycle of the differential clock signal by shifting a DC level of the first clock signal based the first correction signal, and shifting a DC level of the second clock signal based upon the second correction signal.
A system comprising
- a differential clock to generate a differential clock signal comprising a first clock signal and a second clock signal, and
- a clock correction circuit to generate a corrected differential clock signal with the first clock signal and the second clock signal DC level shifted such that the corrected differential clock signal substantially has a predetermined duty cycle.
Dependencies are inferred from the claim text.